代码搜索结果
找到约 10,000 项符合
Logic Analyzer 的代码
leon_eth_pci.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library
ahbram.vhd
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 2003 Gaisler Research
--
-- This library is free soft
f1_zb.vhd
--------0度相位载波--------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity f1_zb is
port (clk :in std_logic;
dout :ou
mux.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux is
port (q1,q2 :in std_logic_vector (7 downto 0);
m :in std_logic;
f2_zb.vhd
--------0度相位载波--------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity f2_zb is
port (clk :in std_logic;
dout :ou
testbench.vhd
library ieee;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity testbench is
end testbench;
x95288xl.vhd
--Use X95288XL complete qlb4.0 logic;
--author bozhang;
--2007.04.20
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity x95288xl is
port
(
--
reg32.vhd
library ieee;
use ieee.std_logic_1164.all;
entity reg32 is
port(load:in std_logic;
datain:in std_logic_vector(31 downto 0);
dataout:out std_logic_vector(31 downto 0));
end entity;
scan.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity scan is
port(indata:in std_logic_vector(31 downto 0);
clk:in std_logic;
control:out integer
triangle1.vhd
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity triangle1 is port(
clk: in std_logic;
data: out std_logic_vector(7 downto 0));
end entity triangle1;
arc