f2_zb.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 33 行

--------0度相位载波--------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity f2_zb is
port (clk    :in  std_logic; 
      dout   :out std_logic_vector(7 downto 0));      
end  f2_zb;

architecture behav of f2_zb is

component rom16_1
         port(address   : in std_logic_vector(3 downto 0);
              inclock   : in std_logic;
              q         : out std_logic_vector(7 downto 0));
end component;

signal count  :  std_logic_vector(3 downto 0);

begin

process(clk)
begin
if clk'event and clk='1' then 
   count<=count+1;     --产生地址         
end if ;                 
end process;
u1 : rom16_1 port map(address=>count,inclock=>clk,q=>dout);--调用ROM表
end architecture behav;