📄 x95288xl.vhd
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--Use X95288XL complete qlb4.0 logic;
--author bozhang;
--2007.04.20
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity x95288xl is
port
(
--signal related with system:
m16M,m4M,m8K : in std_logic; --From vsb board;
xreset,sreset : in std_logic; --extern bus reset and system reset;
sel1,sel2,sel3 : in std_logic; --from extern bus ;
wdog : out std_logic; --watch dog ,timer rotate;
selhdlc : out std_logic; --enable 4 channel 8M HW input, 0(active);
selhw : out std_logic; --enable 4 channel 8M HW output,0(active);
l8ko : out std_logic; --8K clk to other board;
led1,led2,led3,led4: out std_logic; --4 line light;
led8k : out std_logic; --8K indicate light, 0 lighted;
led16m : out std_logic; --16M indicate light,0 lighted;
led4m : out std_logic; --4M indacate light, 0 lighted;
lederr : out std_logic; --sigle board error indicate light;
ledhdlc : out std_logic; --hdlc error indicate light;
--signal related with peripheral device:
ccwr :out std_logic; --peripheral device read/write signal;
ccrd :out std_logic; --peripheral device enable output sigal;
csram :out std_logic; --sram chip enable;
cdpcsl :out std_logic; --dpram left channel chip enable;
--signal related with cpu 5409:
cpurw :in std_logic; --5409 read/write signal; 0(write),1(read);
cds :in std_logic; --5409 data memory enable,0(active);
cmstrb :in std_logic; --5409 strobe signal, 0(active);
clkout :in std_logic; --from 5409;
saddr :in std_logic_vector(15 downto 0);--cbus addr;
sdata :inout std_logic_vector(15 downto 0); --cbus data;
int0,int1,int2,int3:out std_logic; --to 5409 interrupt;
ready :out std_logic; --to 5409 signal to be transmit ready,1(active);
cpu_res :out std_logic; --reset 5409;
--signal related with fpga apa450:
intout : in std_logic; --apa450 input interrupt;
fpga_16M,fpga_4M,fpga_8K: out std_logic; --to fpga apa450 clk;
reset_fpga : out std_logic; --cpld reset apa450;
--signal related with 82525:
hdlc_int: in std_logic; --from 82525 interrupt;
cw525 : out std_logic; --write 82525;
c8k525 : out std_logic; --82525 frame synchronization signal;
c2m525 : out std_logic; --82525 receive and transmit clock;
crst525 : out std_logic; --reset 82525;
cpcs525 : out std_logic; --82525 chip select;
dirgate : out std_logic; --82525 data bus to cbus data direct;
dgate1 : out std_logic; --82525 data bus to cbus data enable;
--signal related with ds21q59:
ds1_int0,ds2_int0,ds3_int0,ds4_int0 :in std_logic; --4 DS21Q59 input interrupt;
ds1_outa :in std_logic_vector(4 downto 1); --selected output A;
ds2_outa :in std_logic_vector(4 downto 1); --selected output A;
ds3_outa :in std_logic_vector(4 downto 1); --selected output A;
ds4_outa :in std_logic_vector(4 downto 1); --selected output A;
ds1_outb :in std_logic_vector(4 downto 1); --selected output B;
ds2_outb :in std_logic_vector(4 downto 1); --selected output B;
ds3_outb :in std_logic_vector(4 downto 1); --selected output B;
ds4_outb :in std_logic_vector(4 downto 1); --selected output B;
ds1_tsync,ds2_tsync,ds3_tsync,ds4_tsync :out std_logic; --transmit sync;
ds1_rsync,ds2_rsync,ds3_rsync,ds4_rsync :out std_logic; --receive sync;
ds1_sysclk,ds2_sysclk,ds3_sysclk,ds4_sysclk:out std_logic; --transmit/receive system clk;
ds1_tclk,ds2_tclk,ds3_tclk,ds4_tclk :out std_logic; --transmit clk;
ds_we :out std_logic; --DS21Q59 write input;
ds_oe :out std_logic; --DS21Q59 read input;
ds_re :out std_logic; --DS21Q59 read input,with ds_oe;
ds_dir :out std_logic; --direction to DS21Q59 data bus with cbus;
ds_gate :out std_logic; --enable connetion DS21Q59 data bus with cbus;
ds1_ts0,ds2_ts0,ds3_ts0,ds4_ts0 :out std_logic; --DS21Q59 transceiver channel select bit 0;
ds1_ts1,ds2_ts1,ds3_ts1,ds4_ts1 :out std_logic; --DS21Q59 transceiver channel select bit 1;
ds1_fcs,ds2_fcs,ds3_fcs,ds4_fcs :out std_logic --DS21Q59 chip select;
);
end entity x95288xl;
architecture logic of x95288xl is
signal fc00,fc01,fc02,fc03,fc04 :std_logic; --addr decode enable
signal fc05,fc06,fc07,fc08 :std_logic;
signal cd :std_logic_vector(7 downto 0);
signal ccd :std_logic_vector(3 downto 0);
signal dd :std_logic_vector(15 downto 0);
signal dd5,dd6,dd7,dd8 :std_logic_vector(7 downto 0);
signal dd3,dd4,dd24 :std_logic_vector(3 downto 0);
signal dd22 :std_logic_vector(1 downto 0);
signal dde :std_logic; --cbus output enable;
signal cwd,ds :std_logic; --peripheral device read/write signal;
signal hdlc_int0 :std_logic; --525 interrupt;
signal ds1_cs,ds2_cs,ds3_cs,ds4_cs :std_logic;
signal ds1_int,ds2_int,ds3_int,ds4_int:std_logic;
signal p8k,p16m :std_logic;
signal intout1 :std_logic;
signal ccs525 :std_logic;
signal rw :std_logic;
signal nreset,reset :std_logic;
signal q0,q1,q2,cmt4m :std_logic;
signal cwr,crd,mstrb :std_logic;
signal bd :std_logic_vector(4 downto 0);
signal reg_fc04 :std_logic_vector(7 downto 0);
signal reg_fc05,reg_fc06,reg_fc07 :std_logic_vector(7 downto 0);
signal reg_fc03,reg_fc02 :std_logic_vector(3 downto 0);
signal reg_fc02s :std_logic_vector(1 downto 0);
signal rclk :std_logic;
signal counter1 :std_logic_vector(7 downto 0); --general 8k clk counter
signal counter2 :std_logic_vector(23 downto 0); --16M clk light
--signal counter3 :std_logic_vector(21 downto 0); --4M clk light
--signal counter4 :std_logic_vector(12 downto 0); --8K clk light
signal counter5 :std_logic_vector(8 downto 0); --525 clk generator counter
signal c2m525s :std_logic;
signal c8k5251 :std_logic;
signal c8k5252 :std_logic;
signal counter6 :std_logic_vector(8 downto 0);
signal ds_2m,ds_8k :std_logic;
signal res_fpga :std_logic;
signal cmt4m0 :std_logic;
signal m16m0,m16m00,m16m000 :std_logic;
signal saddrs :std_logic_vector(7 downto 0);
begin
--address decode
saddrs <= saddr(15 downto 8);
ccs525 <='0' when ((saddrs>=X"E0") and (saddrs<=X"E3") and (ds='0')) else '1';
ds1_cs <='0' when ((saddrs>=X"E4") and (saddrs<=X"E7") and (ds='0')) else '1';
ds2_cs <='0' when ((saddrs>=X"E8") and (saddrs<=X"EB") and (ds='0')) else '1';
ds3_cs <='0' when ((saddrs>=X"EC") and (saddrs<=X"EF") and (ds='0')) else '1';
ds4_cs <='0' when ((saddrs>=X"F0") and (saddrs<=X"F3") and (ds='0')) else '1';
cdpcsl <='0' when ((saddrs>=X"A0") and (saddrs<=X"BF") and (ds='0')) else '1';
csram <='0' when ((saddrs>=X"80") and (saddrs<=X"9F") and (ds='0')) else '1';
fc00 <='1' when ((saddr=X"FC00") and (ds='0')) else '0'; --reset sab82525 enable;
fc01 <='1' when ((saddr=X"FC01") and (ds='0')) else '0'; --reset apa450 enable;
fc02 <='1' when ((saddr=X"FC02") and (ds='0')) else '0';
fc03 <='1' when ((saddr=X"FC03") and (ds='0')) else '0';
fc04 <='1' when ((saddr=X"FC04") and (ds='0')) else '0';
fc05 <='1' when ((saddr=X"FC05") and (ds='0')) else '0';
fc06 <='1' when ((saddr=X"FC06") and (ds='0')) else '0';
fc07 <='1' when ((saddr=X"FC07") and (ds='0')) else '0';
fc08 <='1' when ((saddr=X"FC08") and (ds='0')) else '0';
-----------------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------------
--cbus read/write bus
rw <=cpurw;
mstrb <=cmstrb;
cwr <=mstrb or rw;
crd <=mstrb or (not rw);
ds <=cds;
ready <='1';
ccwr <=cwr;
ccrd <=crd;
------------------------------------------------------------------------------------------
--cbus implementation
dd(1 downto 0) <= dd22;
dd(15 downto 12) <= dd24;
dd(15 downto 12) <= dd3;
dd(15 downto 12) <= dd4;
dd(7 downto 0) <= dd5;
dd(7 downto 0) <= dd6;
dd(7 downto 0) <= dd7;
dd(7 downto 0) <= dd8;
dde <= (not crd) and (fc02 or fc03 or fc04 or fc05 or fc06 or fc07 or fc08);
sdata(15 downto 0) <= dd when ((cwr='1') and (dde='1')) else "ZZZZZZZZZZZZZZZZ";
latch_sdata: process(cwr,sdata) --creat d flop-flip latch input data bus
begin
if cwr'event and cwr='1' then
cd <= sdata(7 downto 0);
ccd<= sdata(15 downto 12);
end if;
end process;
----------------------------------------------------------------------------------------
process(cd,fc00,fc01,fc02,fc03,fc07,nreset,cwr) --write register
begin
if (nreset='1') then
crst525 <= '0';
res_fpga <= '0';
reg_fc02 <= "0000";
reg_fc03 <= "0000";
reg_fc02s <= "00";
reg_fc07 <= X"00";
elsif (cwr='1' and cwr'event) then
if (fc00='1') then
crst525 <= not cd(0);
elsif (fc01='1') then
res_fpga <= not cd(0);
elsif (fc02='1') then
reg_fc02 <= ccd;
reg_fc02s <= cd(1 downto 0);
elsif (fc03='1') then
reg_fc03 <= ccd;
elsif (fc07='1') then
reg_fc07 <= cd;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- res_450: process(fc01,cwr,cd(0),reset) --write reset apa450
-- begin
-- if (reset='0') then
-- res_fpga <='0';
-- elsif (fc01='1') then
-- res_fpga <= not cd(0);
-- end if;
-- end process;
reset_fpga <= res_fpga;
----------------------------------------------------------------------------------------
-- process(reset,fc02,cwr,cd) --write fc02 register
-- begin
-- if (reset='0') then
-- reg_fc02 <= X"00";
-- elsif (fc02='1') then
-- reg_fc02 <= cd;
-- end if;
-- end process;
---------------------------------------------------------------------------------------
process(reg_fc02,fc02,crd,reg_fc02s) --read fc02 register
begin
if ((fc02='1') and (crd='0')) then
dd24 <= reg_fc02;
dd22 <= reg_fc02s;
else
dd24 <= "ZZZZ";
dd22 <= "ZZ";
end if;
end process;
lederr <= reg_fc02s(0);
ledhdlc <= reg_fc02s(1);
led1 <= reg_fc02(0);
led2 <= reg_fc02(1);
led3 <= reg_fc02(2);
led4 <= reg_fc02(3);
--------------------------------------------------------------------------------------
-- process(reset,cd,cwr,fc03) --write fc03 register
-- begin
-- if (reset='1') then
-- reg_fc03 <= X"00";
-- elsif (fc03='1') then
-- reg_fc03 <= cd;
-- end if;
-- end process;
selhdlc <= reg_fc03(1);
selhw <= reg_fc03(2);
wdog <= reg_fc03(3);
-------------------------------------------------------------------------------------
process(fc03,crd,reg_fc03) --read fc03 register
begin
if ((fc03='1') and (crd='0')) then
dd3 <= reg_fc03;
else
dd3 <= "ZZZZ";
end if;
end process;
-----------------------------------------------------------------------------------
process(fc04,crd,sel1,sel2,sel3) --read fc04 register
begin
if ((fc04='1') and (crd='0')) then
dd4(1) <= sel1;
dd4(2) <= sel2;
dd4(3) <= sel3;
dd4(0) <= '0';
else
dd4(3 downto 0) <= "ZZZZ";
end if;
end process;
----------------------------------------------------------------------------------
process(fc05,crd,ds1_outa,ds2_outa) -- read fc05 register
begin
if ((fc05='1') and (crd='0')) then
dd5(3 downto 0) <= ds1_outa;
dd5(7 downto 4) <= ds2_outa;
else
dd5 <= "ZZZZZZZZ";
end if;
end process;
---------------------------------------------------------------------------------
process(fc06,crd,ds3_outa,ds4_outa) --read fc06 register
begin
if ((fc06='1') and (crd='0')) then
dd6(3 downto 0) <= ds3_outa;
dd6(7 downto 4) <= ds4_outa;
else
dd6 <= "ZZZZZZZZ";
end if;
end process;
---------------------------------------------------------------------------------
-- process(reset,cd,cwr,fc07) --write fc07 register
-- begin
-- if (reset='0') then
-- reg_fc07 <= X"00";
-- elsif (fc07='1') then
-- reg_fc07 <= cd;
-- end if;
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