mux.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux is 
port (q1,q2 :in std_logic_vector (7 downto 0);
      m :in std_logic;
      dout : out std_logic_vector (7 downto 0));
end mux;


architecture mux of mux is 
begin 
process (q1,q2)
begin
case m is 
when '1' => dout<=q1;
when '0' => dout<=q2;
end case ;
end process;
end mux;