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找到约 10,000 项符合
Logic Analyzer 的代码
reject.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reject1 is
Port (clk : in std_logic;
mode : in std_logic;
demo_all.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demo_all is
Port (clk : in std_logic;
mode : in std_logic_vector(5
mode_cymometer.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:33:14 03/25/05
-- Design Name:
-- Module Name: mode_cym
lcd.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_6 is
Port ( clk,rst,ce : in STD_LOGIC;
sf_ce0 : out STD
clk.vhd
library ieee;
use ieee.std_logic_1164.all;
entity clk is
port(clkin:in std_logic;
seg1:out std_logic_vector(3 downto 0);
seg2:out std_logic_vector(3 downto 0);
seg3:out std_logic_vector(3 d
fen60.vhd
-------------------------------------------------
--实体名：fen60
--功 能：60进制计数器
--接 口：clk -时钟输入
-- qout1-个位BCD输出
-- qout2-十位BCD输出
-- carry-进位信号输出
--作 者：Haibing Li
--日 期：
qwe1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder38 is
port (Q0: out std_logic_vector(7 downto 0);
Q1: in std_logic_vector(2 downto 0);
g1,g2,g3:
reg10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG10B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO
reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT ( Load : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO
mux21s.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX21S IS
PORT (S : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q