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找到约 10,000 项符合
Logic Analyzer 的代码
freq.vhd
LIBRARY IEEE; --4位十进制频率计的顶层文件
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY freq IS
PORT(F_IN,CLKKK:IN STD_LOGIC;
F_COUT:OUT STD_LOGIC;
ZA,ZB,ZC,ZD:OUT S
cnt_up_down.vhd
--------------------------------------------- Licznik binarny, dwukierunkowy
--
-- Licznik binarny, dwukierunkowy, bez zerowania RESET. Warto滄 pocz箃kowa po
-- w彻czeniu napi阠ia zasilania to stan
adder.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(load: in std_logic;
a:in std_logic_vector(15 downto 0);
b:in std_logic_vector(15
hour.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;
architecture hour_
mian.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mian is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
en
minute.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
andarith.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS -- 选通与门模块
PORT ( ABIN : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOU
multi8x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY MULTI8X8 IS -- 8位乘法器顶层设计
PORT ( CLKK,START : IN STD_LOGIC;
A,
efepd.vhd
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
dvf.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DVF IS
PORT( CLK:IN STD_LOGIC;
D :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
FOUT:OUT STD_LOGIC);
END;
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