efepd.vhd

完整的等精度频率相位计

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY efepd IS 
	port
	(
		BCLK :  IN  STD_LOGIC;
		PA :  IN  STD_LOGIC;
		PB :  IN  STD_LOGIC;
		CLR :  IN  STD_LOGIC;
		CL :  IN  STD_LOGIC;
		SPUL :  IN  STD_LOGIC;
		SEL :  IN  STD_LOGIC_VECTOR(2 downto 0);
		START :  OUT  STD_LOGIC;
		EEND :  OUT  STD_LOGIC;
		DATA :  OUT  STD_LOGIC_VECTOR(7 downto 0)
	);
END efepd;

ARCHITECTURE bdf_type OF efepd IS 

component epd
	PORT(PA : IN STD_LOGIC;
		 PB : IN STD_LOGIC;
		 EPD : OUT STD_LOGIC
	);
end component;

component efcount
	PORT(bclk : IN STD_LOGIC;
		 tclk : IN STD_LOGIC;
		 clr : IN STD_LOGIC;
		 cl : IN STD_LOGIC;
		 spul : IN STD_LOGIC;
		 sel : IN STD_LOGIC_VECTOR(2 downto 0);
		 start : OUT STD_LOGIC;
		 eend : OUT STD_LOGIC;
		 data : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;


BEGIN 



b2v_inst : epd
PORT MAP(PA => SYNTHESIZED_WIRE_0,
		 PB => PB,
		 EPD => SYNTHESIZED_WIRE_1);

b2v_inst1 : efcount
PORT MAP(bclk => BCLK,
		 tclk => SYNTHESIZED_WIRE_1,
		 clr => CLR,
		 cl => CL,
		 spul => SPUL,
		 sel => SEL,
		 start => START,
		 eend => EEND,
		 data => DATA);

SYNTHESIZED_WIRE_0 <= NOT(PA);


END;