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Logic Analyzer 的代码
shiftreg7495.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift7495 is
port(clk, cr, rin,lin: in std_logic;
s: in std_logic_vector(
dec7418.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dec74138 is
port(g1,g2,g3: in std_logic;
a: in std_logic_vector(2 downto 0);
y: out
mux74151.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux74151 is
port(en: in std_logic;
a: in std_logic_vector(2 downto 0);
d: in std_lo
mux74151.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mux74151 is
port(en: in std_logic;
a: in std_logic_vector(2 downto 0);
d: in std_lo
shiftreg7495.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift7495 is
port(clk, cr, rin,lin: in std_logic;
s: in std_logic_vector(
unishift74194.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity shift74194 is
port(clk, cr, rin,lin: in std_logic;
s: in std_logic_vector
dec7418.vhd.bak
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity dec74138 is
port(g1,g2,g3: in std_logic;
a: in std_logic_vector(2 downto 0);
y: out
vhdl.txt
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY ad9851 is
port(reset:buffer std_logic;
clk:in std_logic;
data:out std_logic_vector(7 downto 0);
count.vhd
LIBRARY IEEE; --4位十进制计数器（0~9999）
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY count IS
PORT(CLKN,ENN,RSTN:IN STD_LOGIC;
COUTN:OUT STD_LOGIC;
QA,QB,QC,Q
reg16.vhd
LIBRARY IEEE; --16位锁存器
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY reg16 IS
PORT(LK:IN STD_LOGIC;
DIN1,DIN2,DIN3,DIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT1,DOUT2,DOUT3,DOUT4:OUT STD_LO