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Logic Analyzer 的代码
liushuideng.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY liushuideng IS
PORT(
CLK: IN STD_LOGIC;
T:OUT STD_LOGIC_VECTOR(7 DOWNTO 0 )
);
END liushui
liushuideng.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY liushuideng IS
PORT(
CLK: IN STD_LOGIC;
T:OUT STD_LOGIC_VECTOR(7 DOWNTO 0 )
);
END liushui
38.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decorder38 IS
PORT(g1,g2a,g2b:in std_logic;
a,b,c:in std_logic;
y:out std_logic_vector(7 downto 0));
END decorder38;
ARC
lsd.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lsd IS
PORT(
CLK:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END lsd;
ARCHITECTUR
decorder38.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decorder38 IS
PORT(g1,g2a,g2b:in std_logic;
a,b,c:in std_logic;
y:out std_logic_vector(7 downto 0));
END decorder38;
ARC
deng.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY deng IS
PORT(
CLK:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END deng;
ARCHITECT
light.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY light IS
PORT(
CLK:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END light;
ARCHITE
二進位3-bit補述產生器.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--D Flip-Flop
entity dff is
port(CLK, RESET, D : in std_logic;
Q :
bus_51.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BUS_51 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
P0T: OUT STD_LOGIC_VECT
mul2_1.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX2_1 IS
PORT(X1,X2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK:IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END MUX2_1;
ARCHITECTURE ART