二進位3-bit補述產生器.vhd

二進位的補數產生器

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
--D Flip-Flop
entity dff is
  port(CLK, RESET, D : in std_logic;
                  Q : out std_logic);
end dff;

architecture pet_pr of dff is
begin
process (D,CLK, RESET)
  begin
    if (RESET = '1') then
      Q <= '0';
    else
      if (CLK'event and CLK = '1') then
         Q<= D;
      end if;
    end if;
  end process;
end;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;


entity complement is
  port(X, Y, C : in std_logic;
       Z : out std_logic);
end complement;

architecture structural_4 of complement is
  component dff
     port(CLK, RESET, D : in std_logic;
                     Q : out std_logic);
  end component;
signal nX, nY, nQ, a1, b1, c1, d1, Qt : std_logic;
begin
  DFF1 : dff
    port map (C,Y,d1,Qt);
  nQ <= NOT Qt;
  nX <= NOT X;
  nY <= NOT Y;
  a1 <= nX AND Qt;
  b1 <= X AND nQ;
  c1 <= X OR Qt;
  d1 <= nY AND c1;
  Z <= a1 OR b1;
end structural_4;