bus_51.vhd

数字示波器的FPGA实现 VHDL编写 Quartus7.1测试通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BUS_51 IS
PORT(P0I: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     P0T: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     ALE,RD,WR,CLK: IN STD_LOGIC;
     GX,CLR,DY: OUT STD_LOGIC;
     PDATA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     FDATA: OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
     P2: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
     CS: IN STD_LOGIC);
END BUS_51;
ARCHITECTURE ART OF BUS_51 IS

  SIGNAL RAMTMP0: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP1: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP2: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP3: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL RAMTMP4: STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL TMP: STD_LOGIC;
  SIGNAL LATCH_ADDRES: STD_LOGIC_VECTOR(7 DOWNTO 0);
  BEGIN

  PROCESS(ALE)                    
  BEGIN
  IF ALE'EVENT AND ALE='0' THEN
      LATCH_ADDRES<=P0I;
  END IF;
  END PROCESS;

  PROCESS(CLK,RD,CS)
    VARIABLE P0_OUT: STD_LOGIC_VECTOR(7 DOWNTO 0);
  BEGIN
  IF (CLK'EVENT AND CLK='1') THEN
  IF( RD='0')AND (CS='0') THEN
      IF LATCH_ADDRES="11111100" THEN
          GX<='1';
          P0_OUT:=RAMTMP0;
      ELSIF LATCH_ADDRES="11111101" THEN
          GX<='1';
          P0_OUT:=RAMTMP1;
      ELSE GX<='0';
      END IF;
  ELSE GX<='0';
  END IF;
  END IF;
  P0T<=P0_OUT;
  END PROCESS;
  
  PROCESS(CLK,WR,CS)
  BEGIN
  IF (CLK'EVENT AND CLK='0') THEN
    IF ( WR='0')AND (CS='0') THEN
      IF LATCH_ADDRES="11111100" THEN
          RAMTMP0<=P0I;
          TMP<='0';
      ELSIF LATCH_ADDRES="11111101" THEN
          RAMTMP1<=P0I;
          TMP<='0';
      ELSIF LATCH_ADDRES="11111110" THEN
          RAMTMP2<=P0I;
          TMP<='0';
      ELSIF LATCH_ADDRES="11111111" THEN
          RAMTMP3<=P0I;
          TMP<='0';
      ELSIF LATCH_ADDRES="11111011" THEN
          RAMTMP0<="00000000";
          RAMTMP1<="00000000";
          RAMTMP2<="00000000";
          RAMTMP3<="00000000";
          TMP<='1';
      ELSE RAMTMP4<=P0I;
      END IF;
    END IF;
  END IF;
  END PROCESS;
  DY<=P2(0) AND P2(1) AND P2(2) AND P2(3) AND P2(4);
  FDATA(21 DOWNTO 0)<="110010" & RAMTMP0 & RAMTMP1;
  PDATA(7 DOWNTO 0)<=RAMTMP2;
  CLR<=TMP;
  END ART;