📄 light.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY light IS
PORT(
CLK:IN STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END light;
ARCHITECTURE DEC_BEHAVE OF light IS
SIGNAL SEL:INTEGER RANGE 0 TO 7;
BEGIN
PROCESS(CLK,SEL)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
SEL<=SEL+1;
CASE SEL IS
WHEN 0=> Y<="10000000";
WHEN 1=> Y<="01000000";
WHEN 2=> Y<="00100000";
WHEN 3=> Y<="00010000";
WHEN 4=> Y<="00001000";
WHEN 5=> Y<="00000100";
WHEN 6=> Y<="00000010";
WHEN 7=> Y<="00000001";
END CASE;
END IF;
END PROCESS;
END ;
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