📄 38.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY decorder38 IS
PORT(g1,g2a,g2b:in std_logic;
a,b,c:in std_logic;
y:out std_logic_vector(7 downto 0));
END decorder38;
ARCHITECTURE behave OF decorder38 IS
signal indata:std_logic_vector(2 downto 0);
BEGIN
indata<=c&b&a;
PROCESS(indata,g1,g2a,g2b)
BEGIN
IF(g1='1' and g2a='0' and g2b='0') THEN
CASE indata IS
WHEN "000"=>y<="11111110";
WHEN "001"=>y<="11111101";
WHEN "010"=>y<="11111011";
WHEN "011"=>y<="11110111";
WHEN "100"=>y<="11101111";
WHEN "101"=>y<="11011111";
WHEN "110"=>y<="10111111";
WHEN "111"=>y<="01111111";
WHEN others=>y<="XXXXXXXX";
END CASE;
ELSE
y<="11111111";
END if;
END PROSESS;
END behave;
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