deng.vhd

来自「可以轻松实现秒表计数流水灯计数功能控制器」· VHDL 代码 · 共 32 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY deng IS
   PORT(
        CLK:IN STD_LOGIC;
        Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END deng;
ARCHITECTURE DEC_BEHAVE OF light IS
  SIGNAL SEL:INTEGER RANGE 0 TO 7;
BEGIN
   PROCESS(CLK,SEL)
BEGIN
IF CLK'EVENT AND CLK='1'THEN
     SEL<=SEL+1;
CASE SEL IS
  WHEN 0=> Y<="10000000";
  WHEN 1=> Y<="01000000";
  WHEN 2=> Y<="00100000";
  WHEN 3=> Y<="00010000";
  WHEN 4=> Y<="00001000";
  WHEN 5=> Y<="00000100";
  WHEN 6=> Y<="00000010";
  WHEN 7=> Y<="00000001";
   END CASE;
     END IF;
   END PROCESS;
   END ;