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library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity control is port(p0:in std_logic_vector(7 downto 0); ale:in std_logic; wr:in std_logic; a:

--------------------------------------------------------------------------------------------------- -- -- Title : JPEG Hardware Compressor Testbench -- Design : jpeg -- Author : Vi

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity crc is port(clk,reset:in std_logic; q1,q_crc:out std_logic; q2:out std_logic_vector(15 downto 0))

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity crc is port(clk,reset:in std_logic; q1,q_crc:out std_logic; q2:out std_logic_vector(15 downto 0))

library ieee; use ieee.std_logic_1164.all; entity cmbwordtrig is port( data : in std_logic_vector(31 downto 0); tword : in std_logic_vector(31 downto 0); sel : in std_logic_vector(

--下层模块，防抖电路 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity debounce is port( key,cp:in std_logic; imp:out std_logic); en

--锁存器模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity frelatch is port( reset:in std_logic; cp3:in std_logic; overflow:in std_logic; low:in std_log

--上层模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity plj is port( cp_20m:in std_logic;--20MHz时钟信号 enable:in std_logic;--开关信号 input:in std_logic;--输入被测

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bahe is port(clk_4m,man_left,man_right,clr1,judger: in std_logic; judger_out:ou

--****************************************************** LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --*****************************