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Logic Analyzer 的代码
control.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port
(
clk1024,clk500,sa,sb,sc,en: in std_logic;
q1 : in std_logic_vector(7 downto 0);
q2
speed.vhd
--16 mtimes;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY speed IS
PORT(
clk,reset,start : IN STD_LOGIC;
k : IN STD_LOGIC_VECTOR(4 downto 0);
clk
bcdto7seg.vhd
library ieee;
use ieee.std_logic_1164.all;
entity converter is
port(
db:in std_logic_vector(3 downto 0);
seg:out std_logic_vector(6 downto 0)
);
end converter;
architecture a of con
write_reg.vhd
library ieee;
use ieee.std_logic_1164.all;
entity write_reg is port(
ale : in std_logic;
ad_in : in std_logic_vector(7 downto 0);
sa_h : in std_logic_vector(15 downto 8);
csa_2weight.vhd
-- hds header_start
--
-- VHDL Architecture FPdivider24.csa_2weight.untitled
--
-- Created:
-- by - kenboy.UNKNOWN (IBM-BVE1KE4DQ5P)
-- at - 16:08:52 2003/11/26
--
-- Generat
fpdiv_32.vhd
--Floating Point ieee754 Div
-- |---------------------------------------------------------------|
-- | IEEE 754 Floating Point_division. |
-- |
pe_pkg.vhd
------------------------------------------------------------------------
--
-- Copyright (C) 1998-1999, Annapolis Micro Systems, Inc.
-- All Rights Reserved.
--
--------------------------------
tb_progprom_tmpl.vhd
-- VHDL testbench template generated by SCUBA ispLever_v70_SP2_Build (24)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity tb is
end entity tb;
architecture test o
progprom_tmpl.vhd
-- VHDL module instantiation generated by SCUBA ispLever_v70_SP2_Build (24)
-- Module Version: 4.1
-- Mon Mar 10 16:04:11 2008
-- parameterized module component declaration
component ProgPRom
po
pwm_m8.vhd
-----------------------------------------------------------------------
-- PWM_M8.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT