📄 pe_pkg.vhd
字号:
------------------------------------------------------------------------
--
-- Copyright (C) 1998-1999, Annapolis Micro Systems, Inc.
-- All Rights Reserved.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Package : PE_Package
--
-- Library : PEX_Lib
--
-- Filename : pex_pkg.vhd
--
-- Date : 9/3/99
--
-- Description : Contains all record, procedure, and component
-- declarations for basic I/O interfaces particular
-- to PEX of WILDSTAR(tm) boards.
--
------------------------------------------------------------------------
-------------------------- Library Declarations ------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------- Package Declaration ------------------------
package PE_Package is
--
-- Clock Delay Locked Loop (DLL) settings: none (below 25 MHz),
-- low frequency (25 to 90 MHz), or high frequency (60 to 180 MHz)
--
-- type Clk_DLL_Type is ( NONE, LOW_FREQ, HIGH_FREQ );
constant NONE : INTEGER := 0;
constant LOW_FREQ : INTEGER := 1;
constant HIGH_FREQ : INTEGER := 2;
--
-- Output buffer (OBUF) type can be of the following types:
-- slow 12 mA, slow 8 mA, fast 12 mA, or fast 8 mA buffers.
--
-- type OBUF_Drive_Type is ( SLOW_12mA, SLOW_8mA, FAST_12mA, FAST_8mA );
constant SLOW_12mA : INTEGER := 0;
constant SLOW_8mA : INTEGER := 1;
constant FAST_12mA : INTEGER := 2;
constant FAST_8mA : INTEGER := 3;
--
-- Input flip-flops (INFF) can either have their inputs
-- directly from the input buffers or they can be delayed
-- (normally no delay is needed if a DLL is used on the
-- clock used to clock in the data, otherwise delay is used
-- to compensate for clock skew).
--
-- type INFF_Delay_Type is ( NODELAY, DELAY );
constant NODELAY : INTEGER := 0;
constant DELAY : INTEGER := 1;
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
--
-- Pads Types, Components, and Procedures
--
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
----------------------------------------------------------------------
--
-- Clock_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CB : CardBus
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _PE : Processing Element
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Pad Name Width Description
-- ==================== ===== =====================================
-- M_Clk 1 Memory clock
-- P_Clk 1 Processing element clock
-- K_Clk 1 LAD-bus clock
-- U_Clk 1 User clock
--
----------------------------------------------------------------------
type Clock_Pads_Type is record
M_Clk : std_logic;
P_Clk : std_logic;
K_Clk : std_logic;
U_Clk : std_logic;
end record;
procedure Init_Clock_Pads
(
signal Pads : out Clock_Pads_Type
);
----------------------------------------------------------------------
--
-- LAD_Bus_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Description
-- ==================== ===== =====================================
-- Addr_Data 32 Shared address/data bus
-- DS_n 1 Data strobe
-- Reg_n 1 Register mode select
-- WR_n 1 Write select
-- CS_n 1 PE chip select
-- Int_Req_n 1 Interrupt request
-- DMA_Chan 2 DMA channel number indicator
-- DMA_Stat 2 DMA channel status flags
--
----------------------------------------------------------------------
type LAD_Bus_Pads_Type is record
DS_n : std_logic;
Addr_Data : std_logic_vector ( 31 downto 0 );
Reg_n : std_logic;
WR_n : std_logic;
CS_n : std_logic;
Int_Req_n : std_logic;
DMA_Chan : std_logic_vector ( 1 downto 0 );
DMA_Stat : std_logic_vector ( 1 downto 0 );
end record;
procedure Init_LAD_Bus_Pads
(
signal Pads : out LAD_Bus_Pads_Type
);
----------------------------------------------------------------------
--
-- LED_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Description
-- ==================== ===== =====================================
-- Red_n 1 Red light emitting diode output pad
-- Green_n 1 Green light emitting diode output pad
--
----------------------------------------------------------------------
type LED_Pads_Type is record
Red_n : std_logic;
Green_n : std_logic;
end record;
procedure Init_LED_Pads
(
signal Pads : out LED_Pads_Type
);
----------------------------------------------------------------------
--
-- Mem_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Description
-- ==================== ===== =====================================
-- Addr 19 Address bus pads
-- Data 32 Data bus pads
-- Addr_CS_n 1 Address chip select (extra addr line)
-- CS_n 1 Chip select
-- WE_n 1 Write enable
--
----------------------------------------------------------------------
type Mem_Pads_Type is record
Addr : std_logic_vector ( 18 downto 0 );
Data : std_logic_vector ( 31 downto 0 );
Addr_CS_n : std_logic;
CS_n : std_logic;
WE_n : std_logic;
end record;
procedure Init_Mem_Pads
(
signal Pads : out Mem_Pads_Type
);
----------------------------------------------------------------------
--
-- Mezz_Conn_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Description
-- ==================== ===== =====================================
-- Left 89 Left mezzanine connector pads
-- Right 89 Right mezzanine connector pads
--
----------------------------------------------------------------------
type Mezz_Conn_Pads_Type is record
Left : std_logic_vector ( 88 downto 0 );
Right : std_logic_vector ( 88 downto 0 );
end record;
procedure Init_Mezz_Conn_Pads
(
signal Pads : out Mezz_Conn_Pads_Type
);
----------------------------------------------------------------------
--
-- PE0_Bus_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Description
-- ==================== ===== =====================================
-- N/A 2 PE0 bus pads
--
----------------------------------------------------------------------
subtype PE0_Bus_Pads_Type is std_logic_vector ( 1 downto 0 );
procedure Init_PE0_Bus_Pads
(
signal Pads : out PE0_Bus_Pads_Type
);
----------------------------------------------------------------------
--
-- Reset_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Description
-- ==================== ===== =====================================
-- N/A 1 Reset pad
--
----------------------------------------------------------------------
subtype Reset_Pads_Type is std_logic;
procedure Init_Reset_Pads
(
signal Pads : out Reset_Pads_Type
);
----------------------------------------------------------------------
--
-- Systolic_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Description
-- ==================== ===== =====================================
-- N/A 36 Systolic bus data pads
--
----------------------------------------------------------------------
subtype Systolic_Pads_Type is std_logic_vector ( 35 downto 0 );
procedure Init_Systolic_Pads
(
signal Pads : out Systolic_Pads_Type
);
----------------------------------------------------------------------
--
-- PEX_Pads_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Description
-- ==================== ============================================
-- Clocks Clock signal pads
-- LAD_Bus Local address/data bus signal pads
-- Left_Mem Left memory pads
-- Right_Mem Right memory pads
-- Bot_Sys Bottom systolic bus pads
-- Top_Sys Top systolic bus pads
-- Mezz Mezzanine connector pads
-- LEDs Light-emitting diode output pads
-- PE0_Bus PE0 bus pads
--
----------------------------------------------------------------------
type PEX_Pads_Type is record
Clocks : Clock_Pads_Type;
Reset : Reset_Pads_Type;
LAD_Bus : LAD_Bus_Pads_Type;
Left_Mem : Mem_Pads_Type;
Right_Mem : Mem_Pads_Type;
Top_Sys : Systolic_Pads_Type;
Bot_Sys : Systolic_Pads_Type;
Mezz : Mezz_Conn_Pads_Type;
LEDs : LED_Pads_Type;
PE0_Bus : PE0_Bus_Pads_Type;
end record;
procedure Init_PEX_Pads
(
signal Pads : out PEX_Pads_Type
);
component PEX is
generic
(
SYNTHESIS : boolean := TRUE
);
port
(
Pads : inout PEX_Pads_Type
);
end component;
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
--
-- Basic I/O Types, Components, and Procedures
--
--@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
----------------------------------------------------------------------
--
-- Clock_Basic_IO_Type
--
-- Name Key:
-- =========
-- _AS : Address Strobe
-- _CB : CardBus
-- _CE : Clock Enable
-- _CS : Chip Select
-- _DS : Data Strobe
-- _EN : Enable
-- _OE : Output Enable
-- _PE : Processing Element
-- _RD : Read Select
-- _WE : Write Enable
-- _WR : Write Select
-- _d[d...] : Delayed (registered) signal (each 'd' denotes one
-- level of delay)
-- _n : Active low signals (must be last part of name)
--
-- Name Width Dir* Description
-- ==================== ===== ==== ==============================
-- M_Clk 1 I Memory clock
-- P_Clk 1 I Processing element clock
-- K_Clk 1 I LAD-bus clock
-- U_Clk 1 I User clock
--
-- * Direction 'O' means the user drives the signal, 'I' means the
-- pads drive the signal.
--
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -