fpdiv_32.vhd

是Nios II處理器下客製化指令的一個32位元浮點數除法器

--Floating Point ieee754 Div
--   |---------------------------------------------------------------|
--   |   IEEE 754 Floating Point_division.                           |
--   |                                      written by Yu-Chi Lin    |
--   |                                    last modified at 93.07.20  |
--   |---------------------------------------------------------------|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity fpdiv_32 is
  port (
    dataa, datab     : in  std_logic_vector(31 downto 0);
    clk				: in 	std_logic;
    reset			: in 	std_logic;
    clk_en			: in 	std_logic;
    start			: in 	std_logic;
    result        : out std_logic_vector(31 downto 0));
end fpdiv_32;

architecture RTL of fpdiv_32 is

component FPdivider24 
   port( 
      inputa         : IN     std_logic_vector (23 DOWNTO 0);
      inputb         : IN     std_logic_vector (23 DOWNTO 0);
    final_result24	 : OUT    std_logic_vector (27 DOWNTO 0));
end component;
  signal fovf, fundf, fzero 	: std_logic;
   
   
   

   
  signal Xsign, Ysign 			: std_logic; 
  signal Xexp, Yexp 			: std_logic_vector( 7 downto 0);
  signal Xman, Yman				: std_logic_vector(23 downto 0);
  signal Zman       			: std_logic_vector(22 downto 0);
  signal quotient      			: std_logic_vector(27 downto 0);
  signal Xzero, Yzero 			: std_logic;
  signal roundBit				: std_logic;
  signal stickyBit1 			: std_logic;
  signal stickyBit2				: std_logic;
  signal X,Y				    : std_logic_vector(31 downto 0);
  signal clock					: std_logic;

  constant floatZero : std_logic_vector(31 downto 0) := (others=>'0');
    
begin

clock<=clk and clk_en;
process (clock, reset, start)
  begin
   if(reset= '1') then
	   	X<=(others => '0');
   		Y<=(others => '0');
   elsif(clock'event and clock='1') then
   		if(start ='1') then
   			X <= dataa;
   			Y <= datab;
		end if;   	
   end if;
end process;

  Xzero <= '1' when X = floatZero else '0';
  Yzero <= '1' when Y = floatZero else '0';

  Xsign <= X(31); 
  Ysign <= Y(31);
  Xexp <= X(30 downto 23); 
  Yexp <= Y(30 downto 23);
  Xman <= '1' & X(22 downto 0);
  Yman <= '1' & Y(22 downto 0);

fixDiv : FPdivider24 port map (
    inputa     			=> Xman,
    inputb     			=> Yman,
  final_result24		=> quotient);
  
--  quotient <= Xman / Yman;
  stickyBit1	<=	quotient(0) or quotient(1);
  stickyBit2	<=	stickyBit1 or quotient(2);
  
  Zman		<=	quotient(26 downto 4)+1 when quotient(27)='1' and 
  									((quotient(4)='0' and quotient(3)='1' and stickyBit2='1')or
  									(quotient(4)='1' and quotient(3)='1'))  else
			quotient(26 downto 4)		when quotient(27)='1' else
			quotient(25 downto 3)+1		when 
									((quotient(3)='0' and quotient(2)='1' and stickyBit1='1')or
  									(quotient(3)='1' and quotient(2)='1'))  else
			quotient(25 downto 3);
  
  resultAdjust : 
  process(Xexp, Yexp, Xzero, Yzero, Xsign, Ysign, Zman)
  
	variable Zexp1,Zexp2 : std_logic_vector(8 downto 0);
	variable ExpOvf, ExpUndf : std_logic;
 begin
    fovf	<= '0'; 
    fundf	<= '0'; 
    fzero	<= '0';
    ExpOvf	:= '0'; 
    ExpUndf := '0';
    Zexp1 :="000000000";
    Zexp2 :="000000000";

    Zexp1 := (('0' & Xexp)+ 127) - ('0'& Yexp) ;

    if ((Xexp(7)='1' and Yexp(7)='0') and (Zexp1(8)='1' or Zexp1="011111111")) then
    	   if(quotient(27) = '0') then
	    	Zexp2 := Zexp1 - 1;

	    	    if(zexp2/="011111110") then
	    		ExpOvf := '1';
	    	    end if;
	     else
	    	ExpOvf := '1';
	     end if;
    elsif (((Xexp(7)='0' and Yexp(7)='1') and (Zexp1(7)='1' and Zexp1(8)='1')) or Zexp1=0) then
    	ExpUndf := '1';
    elsif(quotient(27) = '0' and quotient(26) = '0') then
	    	Zexp2 := Zexp1 - 1;

	    	if(((Xexp(7)='0' and Yexp(7)='1') and (Zexp1(7)='1' and Zexp1(8)='1')) or Zexp1=0) then
	    		ExpUndf := '1';
	    	end if;
    else
    	Zexp2 := Zexp1;
    end if;

--#####  Final Adjust  #####    	
    if (Xzero = '1') or (Yzero = '1') then		-- result 0
      fzero <= '1';
      result <= (others => '0');
      
    elsif (ExpOvf = '1') then				 	-- overflow
      fovf  <= '1';
      if (Xsign = Ysign) then 					-- set to most positive
		result <= "01111111" & "01111111" & 
				"11111111" & "11111111";
      else                    					-- set to most negative
		result <= "11111111" & "01111111" & 
				"11111111" & "11111111";
      end if;
    elsif (ExpUndf = '1') then 
      result <= (others => '0');
      fundf <= '1'; fzero <= '1';
    else 										-- normal situation
      result <= (Xsign xor Ysign)& Zexp2(7 downto 0) & Zman; 
    end if;
    
  end process;
end RTL;