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cardbus_5632.tb
--------------------------------------------------------------------------------
--
-- File : pci5632_280.tb
-- Last Modification: 08/05/2002
--
-- Created In SpDE Version: SpDE 9.3
-- Author :
main_control.vhd
------------------------------------------------------------------------------
-- Project : Video Capture Control
-- Programmer : Byungchan Son
-- Function : Main Control - 傈眉 葛碘 力绢, 鸥捞怪 炼沥
--
wave-v.vhw
-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 23:32:44 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test B
acs_unit.vhd
-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
-
viterbi_block_pkg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE viterbi_block_pkg IS
TYPE vector_of_std_logic_vector4 IS ARRAY (NATURAL RANGE ) OF std_logic_vector(3 DOWNTO 0);
TYP
acs_unit.vhd
-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
-
viterbi_block_pkg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE viterbi_block_pkg IS
TYPE vector_of_std_logic_vector4 IS ARRAY (NATURAL RANGE ) OF std_logic_vector(3 DOWNTO 0);
TYP
acs_unit.vhd
-- -------------------------------------------------------------
--
-- Module: ACS_Unit
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit
-- Created: 2009-03-24 16:23:50
-- Hierarchy Level: 1
-
viterbi_block_pkg.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE viterbi_block_pkg IS
TYPE vector_of_std_logic_vector4 IS ARRAY (NATURAL RANGE ) OF std_logic_vector(3 DOWNTO 0);
TYP
spwm.vhd
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:06:32 04/17/2009
-- Design Name:
-- Module Name: SPWM - RTL