📄 wave-v.vhw
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-- E:\资料\计算机设计与实践\MYCPU16
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Nov 11 23:32:44 2007
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
-- - Save it as a file with a .vhd extension (i.e. File->Save As...)
-- - Add it to your project as a testbench source (i.e. Project->Add Source...)
--
LIBRARY IEEE;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;LIBRARY UNISIM;USE UNISIM.VCOMPONENTS.ALL;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
ENTITY wave-v IS
END wave-v;
ARCHITECTURE testbench_arch OF wave-v IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
COMPONENT visit_memory
PORT (
PCload : In std_logic;
PCout : In std_logic_vector (15 DOWNTO 0);
IRnew : Out std_logic_vector (15 DOWNTO 0);
clk : In std_logic;
nMRD : In std_logic;
nMWR : In std_logic;
Addr : In std_logic_vector (15 DOWNTO 0);
ALUout : In std_logic_vector (7 DOWNTO 0);
data : Out std_logic_vector (7 DOWNTO 0);
Dbus : InOut std_logic_vector (15 DOWNTO 0);
Abus : Out std_logic_vector (15 DOWNTO 0);
nWR : Out std_logic;
nRD : Out std_logic;
nBLE : Out std_logic;
nBHE : Out std_logic;
nMREQ : Out std_logic
);
END COMPONENT;
SIGNAL PCload : std_logic;
SIGNAL PCout : std_logic_vector (15 DOWNTO 0);
SIGNAL IRnew : std_logic_vector (15 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL nMRD : std_logic;
SIGNAL nMWR : std_logic;
SIGNAL Addr : std_logic_vector (15 DOWNTO 0);
SIGNAL ALUout : std_logic_vector (7 DOWNTO 0);
SIGNAL data : std_logic_vector (7 DOWNTO 0);
SIGNAL Dbus : std_logic_vector (15 DOWNTO 0);
SIGNAL Abus : std_logic_vector (15 DOWNTO 0);
SIGNAL nWR : std_logic;
SIGNAL nRD : std_logic;
SIGNAL nBLE : std_logic;
SIGNAL nBHE : std_logic;
SIGNAL nMREQ : std_logic;
BEGIN
UUT : visit_memory
PORT MAP (
PCload => PCload,
PCout => PCout,
IRnew => IRnew,
clk => clk,
nMRD => nMRD,
nMWR => nMWR,
Addr => Addr,
ALUout => ALUout,
data => data,
Dbus => Dbus,
Abus => Abus,
nWR => nWR,
nRD => nRD,
nBLE => nBLE,
nBHE => nBHE,
nMREQ => nMREQ
);
PROCESS -- clock process for clk,
BEGIN
CLOCK_LOOP : LOOP
clk <= transport '0';
WAIT FOR 10 ns;
clk <= transport '1';
WAIT FOR 10 ns;
WAIT FOR 40 ns;
clk <= transport '0';
WAIT FOR 40 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS -- Process for clk
VARIABLE TX_OUT : LINE;
VARIABLE TX_ERROR : INTEGER := 0;
PROCEDURE CHECK_IRnew(
next_IRnew : std_logic_vector (15 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (IRnew /= next_IRnew) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns IRnew="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, IRnew);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_IRnew);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_data(
next_data : std_logic_vector (7 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (data /= next_data) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns data="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, data);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_data);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Abus(
next_Abus : std_logic_vector (15 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (Abus /= next_Abus) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns Abus="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Abus);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Abus);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_nWR(
next_nWR : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (nWR /= next_nWR) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns nWR="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nWR);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_nWR);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_nRD(
next_nRD : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (nRD /= next_nRD) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns nRD="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nRD);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_nRD);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_nBLE(
next_nBLE : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (nBLE /= next_nBLE) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns nBLE="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nBLE);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_nBLE);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_nBHE(
next_nBHE : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (nBHE /= next_nBHE) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns nBHE="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nBHE);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_nBHE);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_nMREQ(
next_nMREQ : std_logic;
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (nMREQ /= next_nMREQ) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns nMREQ="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, nMREQ);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_nMREQ);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
PROCEDURE CHECK_Dbus(
next_Dbus : std_logic_vector (15 DOWNTO 0);
TX_TIME : INTEGER
) IS
VARIABLE TX_STR : String(1 to 4096);
VARIABLE TX_LOC : LINE;
BEGIN
-- If compiler error ("/=" is ambiguous) occurs in the next line of code
-- change compiler settings to use explicit declarations only
IF (Dbus /= next_Dbus) THEN
STD.TEXTIO.write(TX_LOC,string'("Error at time="));
STD.TEXTIO.write(TX_LOC, TX_TIME);
STD.TEXTIO.write(TX_LOC,string'("ns Dbus="));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Dbus);
STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Dbus);
STD.TEXTIO.write(TX_LOC, string'(" "));
TX_STR(TX_LOC.all'range) := TX_LOC.all;
STD.TEXTIO.writeline(results, TX_LOC);
STD.TEXTIO.Deallocate(TX_LOC);
ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
TX_ERROR := TX_ERROR + 1;
END IF;
END;
BEGIN
-- --------------------
PCload <= transport '0';
PCout <= transport std_logic_vector'("0000000000000000"); --0
nMRD <= transport '0';
nMWR <= transport '0';
Addr <= transport std_logic_vector'("0000000000000000"); --0
ALUout <= transport std_logic_vector'("00000000"); --0
-- --------------------
WAIT FOR 200 ns; -- Time=200 ns
PCload <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=300 ns
PCload <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=400 ns
PCload <= transport '1';
-- --------------------
WAIT FOR 300 ns; -- Time=700 ns
PCload <= transport '0';
-- --------------------
WAIT FOR 100 ns; -- Time=800 ns
PCload <= transport '1';
-- --------------------
WAIT FOR 100 ns; -- Time=900 ns
PCload <= transport '0';
-- --------------------
WAIT FOR 110 ns; -- Time=1010 ns
-- --------------------
IF (TX_ERROR = 0) THEN
STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Simulation successful (not a failure). No problems detected. "
SEVERITY FAILURE;
ELSE
STD.TEXTIO.write(TX_OUT, TX_ERROR);
STD.TEXTIO.write(TX_OUT, string'(
" errors found in simulation"));
STD.TEXTIO.writeline(results, TX_OUT);
ASSERT (FALSE) REPORT
"Errors found during simulation"
SEVERITY FAILURE;
END IF;
END PROCESS;
END testbench_arch;
CONFIGURATION visit_memory_cfg OF wave-v IS
FOR testbench_arch
END FOR;
END visit_memory_cfg;
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