📄 cardbus_5632.tb
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--------------------------------------------------------------------------------
--
-- File : pci5632_280.tb
-- Last Modification: 08/05/2002
--
-- Created In SpDE Version: SpDE 9.3
-- Author : Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--
-- Description :
-- This is the top level test bench for the QL5632-33 reference design.
-- It instantiates the pci5632_280 module, along with a PCI arbiter, a PCI
-- master, a PCI target, a PCI bus monitor, and an external IDT FIFO model.
-- In the main simulation loop, it includes a PCI command test, a
-- byte-enable generation test, regular DMA tests, and the PCI compliance
-- target test suite.
--
-- Hierarchy:
-- This file is the top-level file in simulation.
--
-- History:
-- Date Author Version
-- 02/09/01 Richard Yuan 1.0
-- - Initial release.
-- 06/26/01 Richard Yuan 1.1
-- - Header added to conform to coding standard.
-- August/05/2002 Jens Niemann 1.2
-- - adapted for Ql5632
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.pci_pack.all;
use work.pci_access_package.all;
use work.pci_comp_package.all;
use work.byte_enable_package.all;
use work.pci_cmd_test_package.all;
use work.cardbus_wrapper_test_package.all;
entity t is begin
end t;
architecture t_arch of t is
component tf_pci_master IS
PORT (
pci_clk : IN std_logic;
pci_ad : INOUT std_logic_vector(63 downto 0);
pci_cbe : OUT std_logic_vector(7 downto 0);
par : INOUT std_logic;
par_64 : INOUT std_logic;
frame_l : INOUT std_logic;
irdy_l : INOUT std_logic;
trdy_l : IN std_logic;
stop_l : IN std_logic;
devsel_l : IN std_logic;
idsel : INOUT std_logic;
req64_l : OUT std_logic;
ack64_l : IN std_logic;
req_l : OUT std_logic;
gnt_l : IN std_logic;
reset_l : IN std_logic;
start_bit : IN std_logic;
done_bit : OUT std_logic;
master_addr : IN std_logic_vector(63 downto 0);
master_command : IN std_logic_vector(3 downto 0);
master_addr_parity : IN std_logic;
master_data_parity : IN std_logic;
master_dword_count : IN integer;
master_initial_data_delay : IN integer;
master_next_data_delay : IN integer;
master_bad_parity_phase : IN integer;
master_m64bit : IN std_logic;
master_quiet : IN std_logic;
be_array : IN BYTE_ARRAY_TYPE;
data_array : IN DATA_ARRAY_TYPE;
pass : OUT std_logic;
last_data : OUT std_logic_vector(63 downto 0)
);
END component tf_pci_master;
component pci_arbiter
generic (pci_master_devices : integer :=1);
port (
pci_clk : in std_logic;
request_n : in std_logic_vector(pci_master_devices-1 downto 0);
grant_n : out std_logic_vector(pci_master_devices-1 downto 0);
busy : in std_logic;
reset_n : in std_logic
);
end component;
component pci_tar
generic (
MEM_SIZE : integer := 4096;
BUS_SIZE : integer := 32
);
port (
clk : in std_logic;
pci_ad : inout std_logic_vector(63 downto 0);
c_be_n : in std_logic_vector(7 downto 0);
par : inout std_logic;
par64 : inout std_logic;
frame_n : in std_logic;
irdy_n : in std_logic;
trdy_n : inout std_logic;
devsel_n : inout std_logic;
req64_n : in std_logic;
ack64_n : inout std_logic;
rst_n : in std_logic;
stop_n : inout std_logic;
perr_n : inout std_logic;
random_val : integer := 0;
device_speed : integer := 1;
base_address : std_logic_vector(63 downto 0) := (others => '0');
stop_count : integer := 5;
stop_enable : std_logic := '1';
waitstates_enable : std_logic := '0';
variable_waits : std_logic := '0';
max_waits : integer := 10;
min_waits : integer := 0;
initial_waits : integer := 2;
subsequent_waits : integer := 1;
stop_waits : integer := 2;
retry_count : integer := 10;
enable_retry_count : std_logic := '0';
wrong_par : std_logic := '0';
wrong_par64 : std_logic := '0';
perr_assert : std_logic := '0';
target_abort : std_logic := '0'
);
end component;
component idt_fifo is
port (
lad : inout std_logic_vector(31 downto 0);
pae_n, paf_n : out std_logic;
or_n, ir_n : out std_logic;
hf_n : out std_logic;
fs : in std_logic;
fwft : in std_logic;
ld : in std_logic;
rt : in std_logic;
mrs, prs : in std_logic;
ren, wen : in std_logic;
oe : in std_logic;
lclk : in std_logic
);
end component idt_fifo;
-- ct added CIS component
component CIS is
port (
pad_CIS_ADR : in std_logic_vector(9 downto 2);
pad_CIS_data : out std_logic_vector(31 downto 0)
);
end component CIS;
component clk_gen is
port (s0,s1 : in std_logic;
lclk : out std_logic;
stop : in boolean
);
end component clk_gen;
COMPONENT proto_chk
PORT (
CLK : in std_logic;
RSTN : in std_logic;
FRAMEN : in std_logic;
IRDYN : in std_logic;
TRDYN : in std_logic;
DEVSELN : in std_logic;
STOPN : in std_logic;
SERRN : in std_logic;
PERRN : in std_logic;
SERRN_Detected : out std_logic;
PERRN_Detected : out std_logic;
Clear_SERR : in std_logic;
Clear_PERR : in std_logic;
Set_Master_Abort : in std_logic;
Master_Abort : out std_logic;
Clear_Disconnect : in std_logic;
Disconnect_Detected : out std_logic;
Status : in boolean
);
END COMPONENT;
COMPONENT cmd_monitor
port (
ad : in std_logic_vector(63 downto 0);
cben : in std_logic_vector(7 downto 0);
clk : in std_logic;
devseln : in std_logic;
framen : in std_logic;
idsel : in std_logic;
irdyn : in std_logic;
par : in std_logic;
perrn : in std_logic;
rstn : in std_logic;
serrn : in std_logic;
stopn : in std_logic;
trdyn : in std_logic;
test_type : in std_logic_vector(7 downto 0);
cmd_mon : out std_logic_vector(7 downto 0)
);
END COMPONENT;
component cardbus_5632
Port (
ir_n : In STD_LOGIC;
mrs : Out STD_LOGIC;
or_n : In STD_LOGIC;
pae_n : In STD_LOGIC;
paf_n : In STD_LOGIC;
REQN : Out STD_LOGIC;
SERRN : Out STD_LOGIC;
PERRN : InOut STD_LOGIC;
PAR : InOut STD_LOGIC;
GNTN : In STD_LOGIC;
STOPN : InOut STD_LOGIC;
IDSEL : In STD_LOGIC;
DEVSELN : InOut STD_LOGIC;
RSTN : In STD_LOGIC;
TRDYN : InOut STD_LOGIC;
CLK : In STD_LOGIC;
IRDYN : InOut STD_LOGIC;
FRAMEN : InOut STD_LOGIC;
CBEN : InOut STD_LOGIC_VECTOR (3 downto 0);
AD : InOut STD_LOGIC_VECTOR (31 downto 0);
lclk : In STD_LOGIC;
ren : Out STD_LOGIC;
oe : Out STD_LOGIC;
wen : Out STD_LOGIC;
ld : Out STD_LOGIC;
lad : InOut STD_LOGIC_VECTOR (31 downto 0);
led : Out STD_LOGIC_VECTOR (7 downto 0);
INTAN : Out STD_LOGIC;
-- ctadded CardBus IP signals
pad_CIS_data : In STD_LOGIC_VECTOR (31 downto 0);
pad_BAM : In STD_LOGIC;
pad_PWM : In STD_LOGIC;
pad_bvd : In STD_LOGIC_VECTOR (2 downto 1);
pad_CBLOCK_n : In STD_LOGIC;
pad_clk_resume : In STD_LOGIC;
pad_gwake : In STD_LOGIC;
pad_intr : In STD_LOGIC;
pad_ready : In STD_LOGIC;
pad_wp : In STD_LOGIC;
pad_CAUDIO : Out STD_LOGIC;
pad_CINT_n : Out STD_LOGIC;
pad_clk_stopped : Out STD_LOGIC;
pad_CSTSCHG : Out STD_LOGIC;
pad_locked : Out STD_LOGIC;
pad_owner_access: Out STD_LOGIC;
pad_CCLKRUN_n : InOut STD_LOGIC;
pad_CIS_ADR : Out STD_LOGIC_VECTOR(9 downto 2)
);
end component;
-- PCI bus signals
signal AD : std_logic_vector(63 downto 0);
signal CBEN : std_logic_vector(7 downto 0);
signal FRAMEN : std_logic;
signal IRDYN : std_logic;
signal TRDYN : std_logic;
signal DEVSELN : std_logic;
signal STOPN : std_logic;
signal PAR : std_logic;
signal PERRN : std_logic;
signal SERRN : std_logic;
signal IDSEL : std_logic;
signal REQN : STD_LOGIC;
signal GNTN : STD_LOGIC;
signal CLK : std_logic;
signal RSTN : std_logic;
-- Unused PCI Signals (64-bit and other)
signal PAR64 : std_logic;
signal REQ64N : std_logic;
signal ACK64N : std_logic;
signal sbo : STD_LOGIC;
signal sdone : STD_LOGIC;
signal lock : STD_LOGIC;
signal intd : STD_LOGIC;
signal intc : STD_LOGIC;
signal intb : STD_LOGIC;
signal INTAN : STD_LOGIC;
-- master1 signals
SIGNAL master1_req_l : std_logic;
SIGNAL master1_gnt_l : std_logic;
SIGNAL master1_start_bit : std_logic := '0';
SIGNAL master1_done_bit : std_logic;
SIGNAL master1_addr : std_logic_vector(63 downto 0);
SIGNAL master1_command : std_logic_vector(3 downto 0);
SIGNAL master1_dword_count : integer := 0;
SIGNAL master1_initial_data_delay : integer;
SIGNAL master1_next_data_delay : integer;
SIGNAL master1_bad_parity_phase : integer;
SIGNAL master1_m64bit : std_logic;
SIGNAL master1_quiet : std_logic;
SIGNAL master1_be_array : BYTE_ARRAY_TYPE;
SIGNAL master1_data_array : DATA_ARRAY_TYPE;
SIGNAL master1_pass : std_logic;
SIGNAL master1_last_data : std_logic_vector(63 downto 0);
-- master2 signals
SIGNAL master2_req_l : std_logic;
SIGNAL master2_gnt_l : std_logic;
SIGNAL master2_start_bit : std_logic := '0';
SIGNAL master2_done_bit : std_logic;
SIGNAL master2_addr : std_logic_vector(63 downto 0);
SIGNAL master2_command : std_logic_vector(3 downto 0);
SIGNAL master2_dword_count : integer := 0;
SIGNAL master2_initial_data_delay : integer;
SIGNAL master2_next_data_delay : integer;
SIGNAL master2_bad_parity_phase : integer;
SIGNAL master2_m64bit : std_logic;
SIGNAL master2_quiet : std_logic;
SIGNAL master2_be_array : BYTE_ARRAY_TYPE;
SIGNAL master2_data_array : DATA_ARRAY_TYPE;
SIGNAL master2_pass : std_logic;
SIGNAL master2_last_data : std_logic_vector(63 downto 0);
-- ct added additional signals based on Eric's test bench
signal mst_ctrl : MASTER_CTRL_TYPE;
signal mst_req : MASTER_REQ_TYPE;
signal mst_resp : MASTER_RESP_TYPE;
-- target1 signals
constant target1_MEMSIZE: integer := 8192;
constant target1_BUS_SIZE: integer := 32;
signal target1_RANDOMVAL: integer := 23;
signal target1_DEVICE_SPEED: integer := 2;
signal target1_BASE_ADDRESS: std_logic_vector(63 downto 0) := x"0000000011110000";
signal target1_STOP_COUNT: integer := 5;
signal target1_STOP_ENABLE: std_logic := '0';
signal target1_WAITSTATES_ENABLE: std_logic := '0';
signal target1_VARIABLE_WAITS: std_logic := '0';
signal target1_MAX_WAITS: integer := 8;
signal target1_MIN_WAITS: integer := 0;
signal target1_INITIAL_WAITS: integer := 1;
signal target1_SUBSEQUENT_WAITS: integer := 2;
signal target1_STOP_WAITS: integer := 5;
signal target1_RETRY_COUNT: integer := 2;
signal target1_ENABLE_RETRY_COUNT: std_logic := '0';
signal target1_WRONG_PAR: std_logic := '0';
signal target1_PERR_ASSERT: std_logic := '0';
signal target1_TARGET_ABORT: std_logic := '0';
-- arbiter signals
CONSTANT PCI_MASTER_DEVICES : integer := 3;
SIGNAL busy : std_logic;
-- simulation constants
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