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Logic Analyzer 的代码
ramdatareg.vhd
--**********************************************************************************************
-- RAM data register for the AVR Core
-- Version 0.1
-- Modified 02.11.2002
-- Designed by Ruslan Lepe
counter60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter60 is
port(clk: in std_logic;
en: in std_logic;
co :out std_logi
clock_2.vhd
-------------------------------fenpinqi----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter2 is
pbclk.vhd
-------------------pbclk------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity pbclk is
port(a: in std
counter100.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter100 is
port(clk: in std_logic;
en: in std_logic;
co :out std_log
counter24.vhd
------------------------------shijian-----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter24 is
port(clk:
div.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity div is
port(clk:in std_logic; --clk:1MHZ
y:buffer std_logic); -- y:1M/2000=500HZ
end div;
arch
t32.cmp
-- Generated by PCI Compiler 3.2.0 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-
seven_seg_pio.vhd
--Copyright (C) 1991-2004 Altera Corporation
--Any megafunction design, and related net list (encrypted or decrypted),
--support information, device programming or simulation file, and any other
--
etester.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY etester IS
PORT (
BCLK : IN STD_LOGIC; --标准频率时钟信号clock2，50MHZ
TCLK : IN STD_LOGIC; --待测频率时钟信号