t32.cmp

Altera的MAXIICPLD模拟PCI接口的Verilog代码

-- Generated by PCI Compiler 3.2.0 [Altera, IP Toolbench v1.2.5 build28]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2004 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

component t32
	PORT (
		clk	: IN STD_LOGIC;
		rstn	: IN STD_LOGIC;
		idsel	: IN STD_LOGIC;
		l_adi	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
		lt_rdyn	: IN STD_LOGIC;
		lt_abortn	: IN STD_LOGIC;
		lt_discn	: IN STD_LOGIC;
		lirqn	: IN STD_LOGIC;
		cben	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		framen	: IN STD_LOGIC;
		irdyn	: IN STD_LOGIC;
		intan	: OUT STD_LOGIC;
		serrn	: OUT STD_LOGIC;
		l_adro	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		l_dato	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		l_beno	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		l_cmdo	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		lt_framen	: OUT STD_LOGIC;
		lt_ackn	: OUT STD_LOGIC;
		lt_dxfrn	: OUT STD_LOGIC;
		lt_tsr	: OUT STD_LOGIC_VECTOR (11 DOWNTO 0);
		cmd_reg	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
		stat_reg	: OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
		perrn	: OUT STD_LOGIC;
		devseln	: OUT STD_LOGIC;
		trdyn	: OUT STD_LOGIC;
		stopn	: OUT STD_LOGIC;
		ad	: INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);
		par	: INOUT STD_LOGIC
	);
end component;