readme.txt

来自「Altera的MAXIICPLD模拟PCI接口的Verilog代码」· 文本 代码 · 共 5 行

This directory has the rtl (Verilog) associated with the MAX II PCI reference design. 
top_pci32.v is the top level of the design. The core directory contains the wizard 
generated files for the 32-bit/33 MHz PCI Target.
The local directory has all the files for local reference design.