div.vhd

本程序是用VHDL编写

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity div is		
	port(clk:in std_logic;		  --clk:1MHZ
		   y:buffer std_logic);	  --  y:1M/2000=500HZ
end div;

architecture div of div is

	
begin
process(clk)
variable count:integer range 0 to 1;
begin
	if(clk'event and clk='1') then		
		if count=1 then		
			count:=0;	
			y<=not y;				
		else 
		count:=count+1;
		end if;
	end if;
end process;
end ;