sm.vhd

来自「本程序是用VHDL编写」· VHDL 代码 · 共 47 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity sm is		            
	port(clk:in std_logic;		
		  ho:out std_logic_vector(7 downto 0);		
		  lo:out std_logic_vector(7 downto 0));		
end sm;

architecture sm of sm is
	signal cnt:std_logic_vector(12 downto 0):="0000000000000";		
	signal counth:std_logic_vector(2 downto 0):="000";		
	signal countl:std_logic_vector(2 downto 0):="000";		
begin
process(clk)
	begin
		if(clk'event and clk='1')then		
			cnt<=cnt+1;
			end if;
		counth(2 downto 0)<=cnt(12 downto 10);			
			case counth(2 downto 0) is
				when"000"=>ho<="10000000";		
				when"001"=>ho<="01000000";		
				when"010"=>ho<="00100000";		
				when"011"=>ho<="00010000";		
				when"100"=>ho<="00001000";		
				when"101"=>ho<="00000100";		
				when"110"=>ho<="00000010";		
				when"111"=>ho<="00000001";		
				when others=>ho<="00000000";		
			end case;
		countl(2 downto 0)<=cnt(9 downto 7);
			case countl(2 downto 0) is
				when"000"=>lo<="01111111";		
				when"001"=>lo<="10111111";		
				when"010"=>lo<="11011111";		
				when"011"=>lo<="11101111";		
				when"100"=>lo<="11110111";		
				when"101"=>lo<="11111011";		
				when"110"=>lo<="11111101";		
				when"111"=>lo<="11111110";		
				when others=>lo<="11111111";		
			end case;
end process;
end ;