clock_2.vhd

VHDL的数字电子钟程序

-------------------------------fenpinqi----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter2 is 
port(clk: in std_logic;
      en: in std_logic;
      output: out std_logic);
end counter2;
architecture a of counter2 is
signal temp:std_logic_vector(3 downto 0);
begin
p1:process(clk)
  begin
    if(temp="0001")then output<='0';
     else output<='1';
     end if;
  end process;
 p2:process(clk,en)
  begin 
     if(en='1')then temp<="0000";
     elsif(clk'event and clk='1')then 
      if(temp="0001")then temp<="0000";
       else temp<=temp+1;
      end if; 
     end if;
   end process;   
end a;
---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;

entity counter10 is 
port(clk: in std_logic;
      en: in std_logic;
      output: out std_logic);
end counter10;
architecture a of counter10 is
signal temp:std_logic_vector(3 downto 0);
begin
p1:process(clk)
  begin
    if(temp<"0101")then output<='0';
     elsif(temp<"1000")then output<='1';
     else output<='1';
     end if;
  end process;
 p2:process(clk,en)
  begin 
     if(en='1')then temp<="0000";
     elsif(clk'event and clk='1')then 
      if(temp="1001")then temp<="0000";
       else temp<=temp+1;
      end if; 
     end if;
   end process;   
end a;
---------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter100 is 
port(clk: in std_logic;
      en: in std_logic;
      co :out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end counter100;
architecture a of counter100 is
signal high1,low1:std_logic_vector(3 downto 0);
begin
process(clk,en)
  begin 
    if(en='1')then low1<="0000";
                   high1<="0000";
     elsif(clk'event and clk='1')then 
      if(high1="1001" and low1="1001")then high1<="0000";
                                           low1<="0000";
                                           co<='1';
        elsif(low1="1001")then  low1<="0000";
                               high1<=high1+1;
          else low1<=low1+1;co<='0';
       end if;
    end if;
    high<=high1; low<=low1;
  end process;   
end a;
----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;

entity fenpinqi is
port(clk:in std_logic;
     clk_500hz:out std_logic;
     clk_1hz:out std_logic;
     pm_h: out std_logic_vector(3 downto 0);
     pm_l:  out std_logic_vector(3 downto 0));
end fenpinqi;
architecture a of fenpinqi is
component counter2 
port(clk: in std_logic;
      en: in std_logic;
      output: out std_logic);
end component;
component counter10  
port(clk: in std_logic;
      en: in std_logic;
      output: out std_logic);
end component;
component counter100  
port(clk: in std_logic;
      en: in std_logic;
      co :out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end component;
signal temp,clk_100hz:std_logic;
begin
 temp<='0';
 u1:counter2 port map(clk,temp,clk_500hz);
 u2:counter10 port map(clk,temp,clk_100hz);
 u3:counter100 port map(clk_100hz,temp,clk_1hz,pm_h,pm_l);
end a;
------------------------------------------------------------------------
-------------------pbclk------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity pbclk is 
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     cp: in std_logic;
     clk: out std_logic);
end pbclk;
architecture a of pbclk is
begin
 process(a,b,c)
 begin 
 if((a='0' and b='1') and c='0')then clk<='0';
 elsif((a='0' and b='0') and c='1')then clk<='0'; 
 else clk<=cp;
 end if;
 end process;
end a;
--------------------------kzyima------------------------------ 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity kzyima is
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     mx: out std_logic;
     en: out std_logic;
     tx: out std_logic;
     k1: out std_logic;
     k2: out std_logic);
end kzyima;
architecture a of kzyima is
begin
 process(a,b,c)
  begin
   if((a='0' and b='0') and c='0')then 
      mx<='0'; en<='0'; k1<='0'; k2<='0';
   elsif((a='0' and b='0') and c='1')then 
      mx<='0'; en<='0'; k1<='1'; k2<='0';
   elsif((a='0' and b='1') and c='0')then 
      mx<='0'; en<='0'; k1<='0'; k2<='1';
   elsif((a='1' and b='0') and c='0')then 
      mx<='1'; en<='0'; tx<='0'; k1<='0'; k2<='0';
   elsif((a='1' and b='0') and c='1')then 
      mx<='1'; en<='1'; tx<='0'; k1<='0'; k2<='0';
   elsif((a='1' and b='1') and c='0')then 
      mx<='1'; en<='1'; tx<='1'; k1<='0'; k2<='0';
   else mx<='0'; en<='0'; k1<='0'; k2<='0';
   end if;
end process;
end a;  
---------------------------sheding--------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity sheding is 
port(clk_tiao: in std_logic;
      tx: in std_logic;
      en: in std_logic;
      h_high: out std_logic_vector(3 downto 0);
      h_low:  out std_logic_vector(3 downto 0);
      m_high: out std_logic_vector(3 downto 0);
      m_low:  out std_logic_vector(3 downto 0);
      s_high: out std_logic_vector(3 downto 0);
      s_low:  out std_logic_vector(3 downto 0));
end sheding;
architecture a of sheding is
signal high1,low1,high2,low2:std_logic_vector(3 downto 0);
signal clk_tiao1: std_logic;
begin
p1:process(clk_tiao,en)
   begin
    s_high<="0000"; 
    s_low<="0000";
    if(en='0')then clk_tiao1<='0';
    else clk_tiao1<=clk_tiao;
    end if;
   end process; 
p2:process(clk_tiao1,tx)
  begin
    if(tx='0')then null;
    elsif(clk_tiao1'event and clk_tiao1='1')then 
      if(high1="0010" and low1="0011")then high1<="0000";
                                           low1<="0000";
        elsif(low1="1001")then  low1<="0000";
                               high1<=high1+1;
          else low1<=low1+1;
       end if;
    end if;
  h_high<=high1;h_low<=low1;
  end process;
p3:process(clk_tiao1,tx)
  begin
    if(tx='1')then null;
    elsif(clk_tiao1'event and clk_tiao1='1')then 
      if(high2="0101" and low2="1001")then high2<="0000";
                                           low2<="0000";
        elsif(low2="1001")then  low2<="0000";
                               high2<=high2+1;
          else low2<=low2+1;
       end if;
    end if;
   m_high<=high2;m_low<=low2;
  end process;   
end a;
------------------------------shijian-----------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter24 is 
port(clk: in std_logic;
      en: in std_logic;
      co: out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end counter24;
architecture a of counter24 is
signal high1,low1:std_logic_vector(3 downto 0);
begin
 process(clk,en)
  begin 
    if(en='1')then low1<="0000";
                   high1<="0000";
     elsif(clk'event and clk='1')then 
      if(high1="0010" and low1="0011")then high1<="0000";
                                           low1<="0000";
                                           co<='1';
        elsif(low1="1001")then  low1<="0000";
                               high1<=high1+1;
          else low1<=low1+1;co<='0';
       end if;
    end if;
    high<=high1; low<=low1;
  end process;   
end a;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter60 is 
port(clk: in std_logic;