pbclk.vhd

来自「VHDL的数字电子钟程序」· VHDL 代码 · 共 24 行

-------------------pbclk------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity pbclk is 
port(a: in std_logic;
     b: in std_logic;
     c: in std_logic;
     cp: in std_logic;
     clk: out std_logic);
end pbclk;
architecture a of pbclk is
begin
 process(a,b,c)
 begin 
 if((a='0' and b='1') and c='0')then clk<='0';
 elsif((a='0' and b='0') and c='1')then clk<='0'; 
 else clk<=cp;
 end if;
 end process;
end a;