counter60.vhd

VHDL的数字电子钟程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
entity counter60 is 
port(clk: in std_logic;
      en: in std_logic;
      co :out std_logic;
      high: out std_logic_vector(3 downto 0);
      low:  out std_logic_vector(3 downto 0));
end counter60;
architecture a of counter60 is
signal high1,low1:std_logic_vector(3 downto 0);
begin
 process(clk,en)
  begin 
    if(en='1')then low1<="0000";
                   high1<="0000";
     elsif(clk'event and clk='1')then 
      if(high1="0101" and low1="1001")then high1<="0000";
                                           low1<="0000";
                                           co<='1';
        elsif(low1="1001")then  low1<="0000";high1<=high1+1;
          else low1<=low1+1;co<='0';
       end if;
    end if;
    high<=high1; low<=low1;
  end process;   
end a;