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Logic Analyzer 的代码
butterfly1_entity5.vhd
-- -------------------------------------------------------------
--
-- Module: Butterfly1_entity5
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS/Subsystem13/Butterfly1
-- Created: 2009-0
subsystem4.vhd
-- -------------------------------------------------------------
--
-- Module: Subsystem4
-- Simulink Path: hdlcoderviterbi/viterbi_block/ACS Unit/ACS/Subsystem4
-- Created: 2009-03-24 16:23:33
-- Hie
fpu_sqrt.vhd
-------------------------------------------------------------------------------
-- $Id: fpu_sqrt.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
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debug_gti.vhd
-------------------------------------------------------------------------------
-- $Id: debug_gti.vhd,v 1.2 2007/12/13 13:56:42 stefana Exp $
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debug.vhd
-------------------------------------------------------------------------------
-- $Id: debug.vhd,v 1.2 2007/12/05 14:26:23 stefana Exp $
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subtract_with_borrow.vhd
-------------------------------------------------------------------------------
-- $Id: subtract_with_borrow.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
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fpu_conv.vhd
-------------------------------------------------------------------------------
-- $Id: fpu_conv.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
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dds_vhdl.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds_vhdl is
port(clk:in std_logic;
fword:in std_logic_vector(7 downto 0);
pword:in std_logic_ve
fpu_exceptions.vhd
---------------------------------------------------------------------
---- ----
---- FPU
generale.vhf
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-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
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