fpu_sqrt.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: fpu_sqrt.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- fpu_sqrt.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  standard level Xilinx Hotline support, and will only address         **
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--
-------------------------------------------------------------------------------
-- Filename:        fpu_sqrt.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              fpu_sqrt.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2006-11-27    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

library unisim;
use unisim.vcomponents.all;

library IEEE;
use IEEE.std_logic_1164.all;

entity fpu_sqrt is
  port (
    Clk               : in  std_logic;
    Reset             : in  std_logic;
    EX_Op1            : in  DATA_TYPE;
    EX_Sqrt_Op        : in  boolean;
    EX_Start_fpu      : in  boolean;
    EX_PipeRun        : in  boolean;
    MEM_Not_Sqrt_Op   : in  boolean;
    MEM_Sqrt_Done     : out boolean;
    MEM_Sqrt_Exp_4    : out FPU_EXP_TYPE;
    MEM_Sqrt_Result_4 : out FPU_MANT_IGRS_TYPE
    );
end entity fpu_sqrt;

library unisim;
use unisim.vcomponents.all;

architecture IMP of fpu_sqrt is

  signal D_Reg      : std_logic_vector(0 to 24);
  signal R_Reg      : std_logic_vector(0 to 24);
  signal Q_Reg      : std_logic_vector(0 to 24);
  signal addsub_res : std_logic_vector(0 to 24);

  signal addsub_carry : std_logic_vector(0 to 25);
  signal addsub_sel   : std_logic_vector(0 to 24);
  
  signal subtract : std_logic;

  signal exponent_res          : std_logic_vector(0 to 7);

  signal exponent_add_op1        : std_logic_vector(0 to 7);
  constant exponent_add_constant : std_logic_vector(0 to 7) := "00111111"; -- 63
  signal exponent_add          : std_logic_vector(0 to 7);
  signal exponent_add_carry    : std_logic_vector(0 to 8);
  signal exponent_add_sel      : std_logic_vector(0 to 7);

  signal iterations : std_logic_vector(0 to 25);
  
  signal ex_start_sqrt   : boolean;
  signal ex_start_sqrt_1 : boolean;
  signal mem_sqrt_round  : std_logic;
  signal mem_sqrt_sticky : std_logic;

  signal sqrt_reset : boolean;
  
begin  -- architecture IMP

  ex_start_sqrt <= EX_Start_FPU and EX_Sqrt_Op and EX_PipeRun;

  D_Reg_DFF: process (Clk) is
  begin  -- process D_Reg_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        D_Reg <= (others => '0');                  
      else
        if (ex_start_sqrt) then
          if (EX_Op1(8) = '1') then     -- Odd exponent
            D_Reg <= "01" & EX_Op1(IEEE754_SINGLE_MANT_POS);
          else
            D_Reg <= '1' & EX_Op1(IEEE754_SINGLE_MANT_POS) & '0';
          end if;
        else
          -- Iterating
          D_Reg <= D_Reg(2 to 24) & "00";            
        end if;
      end if;
    end if;
  end process D_Reg_DFF;

  SQRT_SM : process (Clk) is
  begin  -- process SQRT_SM
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        MEM_Sqrt_Done <= false;
      else
        subtract   <= not(addsub_res(0));
        iterations <= iterations(iterations'left+1 to iterations'right) & '0';
        if (ex_start_sqrt) then
          iterations(iterations'right) <= '1';
          subtract                     <= '1';
        end if;
        MEM_Sqrt_Done <= false;
        if (iterations(iterations'left) = '1') then
          MEM_Sqrt_Done <= True;
        end if;
      end if;
    end if;
  end process SQRT_SM;
  

  R_Reg_DFF : process (Clk) is
  begin  -- process R_Reg_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') or mem_not_sqrt_op then  -- synchronous reset (active high)
        R_Reg(0 to 24)  <= (others => '0');
      else
        R_Reg(0 to 22) <= addsub_res(2 to 24);
        R_Reg(23)      <= D_Reg(0) xnor D_Reg(1);
        R_Reg(24)      <= not D_Reg(1);
        if (ex_start_sqrt) then
          R_Reg(0 to 24)  <= (others => '0');
        end if;
      end if;
    end if;
  end process R_Reg_DFF;


  Q_Reg_DFF: process (Clk) is
  begin  -- process Q_Reg_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') or (ex_start_sqrt) or mem_not_sqrt_op then               -- synchronous reset (active high)
        Q_Reg <= (others => '0');
      else
        Q_Reg <= Q_Reg(1 to 24) & not(addsub_res(0));
      end if;
    end if;
  end process Q_Reg_DFF;

  addsub_carry(25) <= D_Reg(0) or D_Reg(1);

  AddSub_Gen: for I in 24 downto 0 generate

    addsub_sel(I) <= subtract xor R_Reg(I) xor Q_Reg(I);

    D_MUXCY_L : MUXCY_L
      port map (
        DI => R_Reg(I),                 -- [in  std_logic]
        CI => addsub_carry(I+1),        -- [in  std_logic]
        S  => addsub_sel(I),            -- [in  std_logic]
        LO => addsub_carry(I));         -- [out std_logic]

    D_XORCY : XORCY
      port map (
        LI => addsub_sel(I),            -- [in  std_logic]
        CI => addsub_carry(I+1),        -- [in  std_logic]
        O  => addsub_res(I));           -- [out std_logic]
    
  end generate AddSub_Gen;

  exponent_add_carry(8) <= EX_Op1(8);
  exponent_add_op1 <= '0' & EX_Op1(1 to 7);

  exp_add_gen: for I in 7 downto 0 generate
    exponent_add_sel(I) <= exponent_add_op1(I) xor exponent_add_constant(I);

    D_MUXCY_L : MUXCY_L
      port map (
        DI => exponent_add_op1(I),      -- [in  std_logic]
        CI => exponent_add_carry(I+1),  -- [in  std_logic]
        S  => exponent_add_sel(I),      -- [in  std_logic]
        LO => exponent_add_carry(I));   -- [out std_logic]

    D_XORCY : XORCY
      port map (
        LI => exponent_add_sel(I),            -- [in  std_logic]
        CI => exponent_add_carry(I+1),        -- [in  std_logic]
        O  => exponent_add(I));           -- [out std_logic]
    
  end generate exp_add_gen;

  Exponent_Res_DFF: process (Clk) is
  begin  -- process Exponent_Res_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') then               -- synchronous reset (active high)
        Exponent_Res <= (others => '0');
      else
        if (ex_start_sqrt) then
          Exponent_Res <= exponent_add;
        end if;
      end if;
    end if;
  end process Exponent_Res_DFF;

  MEM_Sqrt_Exp_DFF : process (Clk) is
  begin  -- process MEM_Sqrt_Exp_DFF
    if Clk'event and Clk = '1' then     -- rising clock edge
      if (Reset = '1') or mem_not_sqrt_op then  -- synchronous reset (active high)
        MEM_Sqrt_Exp_4 <= (others => '0');
      else
        MEM_Sqrt_Exp_4 <= Exponent_Res;
      end if;
    end if;
  end process MEM_Sqrt_Exp_DFF;

  MEM_Sqrt_Result_4 <= Q_Reg(0 to 24) & mem_sqrt_round & mem_sqrt_sticky;
  mem_sqrt_round    <= R_Reg(0);
  mem_sqrt_sticky   <= '1' when R_Reg(1 to 22) /= (1 to 22 => '0') else '0';
end architecture IMP;