📄 generale.vhf
字号:
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 9.2i
-- \ \ Application : sch2vhdl
-- / / Filename : Generale.vhf
-- /___/ /\ Timestamp : 12/04/2007 11:23:32
-- \ \ / \
-- \___\/\___\
--
--Command: C:\Xilinx92i\bin\nt\sch2vhdl.exe -intstyle ise -family spartan2 -flat -suppress -w "C:/Documents and Settings/Jernej/Desktop/Termometro_visualizzato_su_VGA_vers.ISE_9.2i/VGAterm/generale.sch" Generale.vhf
--Design Name: generale
--Device: spartan2
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity FTC_MXILINX_generale is
port ( C : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end FTC_MXILINX_generale;
architecture BEHAVIORAL of FTC_MXILINX_generale is
attribute BOX_TYPE : string ;
attribute INIT : string ;
attribute RLOC : string ;
signal TQ : std_logic;
signal Q_DUMMY : std_logic;
component XOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
component FDC
-- synopsys translate_off
generic( INIT : bit := '0');
-- synopsys translate_on
port ( C : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute INIT of FDC : component is "0";
attribute BOX_TYPE of FDC : component is "BLACK_BOX";
attribute RLOC of I_36_35 : label is "R0C0.S0";
begin
Q <= Q_DUMMY;
I_36_32 : XOR2
port map (I0=>T,
I1=>Q_DUMMY,
O=>TQ);
I_36_35 : FDC
port map (C=>C,
CLR=>CLR,
D=>TQ,
Q=>Q_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity generale is
port ( clk88 : in std_logic;
hs : out std_logic;
rgb : out std_logic_vector (5 downto 0);
vs : out std_logic;
onewire : inout std_logic);
end generale;
architecture BEHAVIORAL of generale is
attribute HU_SET : string ;
attribute BOX_TYPE : string ;
signal clk : std_logic;
signal data_out : std_logic_vector (7 downto 0);
signal sn_data : std_logic_vector (47 downto 0);
signal XLXN_4 : std_logic;
signal XLXN_5 : std_logic;
signal XLXN_76 : std_logic_vector (33 downto 0);
signal XLXN_77 : std_logic_vector (9 downto 0);
signal XLXN_78 : std_logic_vector (9 downto 0);
signal XLXN_79 : std_logic_vector (3 downto 0);
signal XLXN_80 : std_logic_vector (8 downto 0);
signal XLXN_81 : std_logic_vector (9 downto 0);
signal XLXN_98 : std_logic_vector (3 downto 0);
signal XLXN_99 : std_logic_vector (3 downto 0);
signal XLXN_100 : std_logic_vector (3 downto 0);
component FTC_MXILINX_generale
port ( C : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end component;
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component caratteri
port ( cifra : in std_logic_vector (3 downto 0);
clk : in std_logic;
line_add : in std_logic_vector (8 downto 0);
dato : out std_logic_vector (33 downto 0));
end component;
component pos_sel
port ( clk : in std_logic;
decimal : in std_logic;
segno : in std_logic;
cfr1 : in std_logic_vector (3 downto 0);
cfr2 : in std_logic_vector (3 downto 0);
cfr3 : in std_logic_vector (3 downto 0);
pixel_add : in std_logic_vector (9 downto 0);
inizio : out std_logic_vector (9 downto 0);
fine : out std_logic_vector (9 downto 0);
cifra : out std_logic_vector (3 downto 0));
end component;
component vga
port ( inizio : in std_logic_vector (9 downto 0);
fine : in std_logic_vector (9 downto 0);
colore : in std_logic;
dato : in std_logic_vector (33 downto 0);
clk : in std_logic;
RGB : out std_logic_vector (5 downto 0);
hs : out std_logic;
vs : out std_logic;
line_add : out std_logic_vector (8 downto 0);
pixel_add : out std_logic_vector (9 downto 0));
end component;
component termometro
port ( clk : in std_logic;
data_out : out std_logic_vector (7 downto 0);
sn_data : out std_logic_vector (47 downto 0);
cfr1 : out std_logic_vector (3 downto 0);
cfr2 : out std_logic_vector (3 downto 0);
cfr3 : out std_logic_vector (3 downto 0);
onewire : inout std_logic);
end component;
attribute HU_SET of XLXI_15 : label is "XLXI_15_0";
begin
XLXI_15 : FTC_MXILINX_generale
port map (C=>clk88,
CLR=>XLXN_5,
T=>XLXN_4,
Q=>clk);
XLXI_16 : VCC
port map (P=>XLXN_4);
XLXI_17 : GND
port map (G=>XLXN_5);
XLXI_21 : caratteri
port map (cifra(3 downto 0)=>XLXN_79(3 downto 0),
clk=>clk,
line_add(8 downto 0)=>XLXN_80(8 downto 0),
dato(33 downto 0)=>XLXN_76(33 downto 0));
XLXI_22 : pos_sel
port map (cfr1(3 downto 0)=>XLXN_100(3 downto 0),
cfr2(3 downto 0)=>XLXN_99(3 downto 0),
cfr3(3 downto 0)=>XLXN_98(3 downto 0),
clk=>clk,
decimal=>data_out(0),
pixel_add(9 downto 0)=>XLXN_81(9 downto 0),
segno=>sn_data(11),
cifra(3 downto 0)=>XLXN_79(3 downto 0),
fine(9 downto 0)=>XLXN_78(9 downto 0),
inizio(9 downto 0)=>XLXN_77(9 downto 0));
XLXI_23 : vga
port map (clk=>clk,
colore=>sn_data(11),
dato(33 downto 0)=>XLXN_76(33 downto 0),
fine(9 downto 0)=>XLXN_78(9 downto 0),
inizio(9 downto 0)=>XLXN_77(9 downto 0),
hs=>hs,
line_add(8 downto 0)=>XLXN_80(8 downto 0),
pixel_add(9 downto 0)=>XLXN_81(9 downto 0),
RGB(5 downto 0)=>rgb(5 downto 0),
vs=>vs);
XLXI_24 : termometro
port map (clk=>clk88,
cfr1(3 downto 0)=>XLXN_100(3 downto 0),
cfr2(3 downto 0)=>XLXN_99(3 downto 0),
cfr3(3 downto 0)=>XLXN_98(3 downto 0),
data_out(7 downto 0)=>data_out(7 downto 0),
sn_data(47 downto 0)=>sn_data(47 downto 0),
onewire=>onewire);
end BEHAVIORAL;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -