debug.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: debug.vhd,v 1.2 2007/12/05 14:26:23 stefana Exp $
-------------------------------------------------------------------------------
-- debug.vhd
-------------------------------------------------------------------------------
--
--                  ****************************
--                  ** Copyright Xilinx, Inc. **
--                  ** All rights reserved.   **
--                  ****************************
--
-------------------------------------------------------------------------------
-- Filename:        debug.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              debug.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/12/05 14:26:23 $
--
-- History:
--   goran  2002-03-21    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity Debug is
  generic (
    C_USE_BARREL           : integer := 1;
    C_USE_DIV              : integer := 1;
    C_USE_HW_MUL           : integer := 1;
    C_USE_FPU              : integer := 0;
    C_USE_MSR_INSTR        : integer := 0;
    C_USE_PCMP_INSTR       : integer := 0;
    C_UNALIGNED_EXCEPTIONS : integer := 0;
    C_ILL_OPCODE_EXCEPTION : integer := 0;
    C_IOPB_BUS_EXCEPTION   : integer := 0;
    C_DOPB_BUS_EXCEPTION   : integer := 0;
    C_IPLB_BUS_EXCEPTION   : integer := 0;
    C_DPLB_BUS_EXCEPTION   : integer := 0;
    C_DIV_ZERO_EXCEPTION   : integer := 0;
    C_FPU_EXCEPTION        : integer := 0;
    C_FSL_EXCEPTION        : integer := 0;
    C_USE_EXTENDED_FSL_INSTR  : integer;
    C_FSL_LINKS            : integer := 1;
    C_PVR                  : integer := 0;
    C_PVR_USER1            : std_logic_vector(0 to 7);
    C_PVR_USER2            : std_logic_vector(0 to 31);
    C_MB_VERSION           : std_logic_vector(0 to 7);
    C_INTERCONNECT         : integer := 0;

    C_USE_ICACHE            : integer                   := 0;
    C_ICACHE_USE_FSL        : integer                   := 0;
    C_ICACHE_BASEADDR       : std_logic_vector(0 to 31) := X"00000000";
    C_ICACHE_HIGHADDR       : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_USE_DCACHE            : integer                   := 0;
    C_DCACHE_USE_FSL        : integer                   := 0;
    C_DCACHE_BASEADDR       : std_logic_vector(0 to 31) := X"00000000";
    C_DCACHE_HIGHADDR       : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_TARGET                : TARGET_FAMILY_TYPE;
    C_DATA_SIZE             : natural range 4 to 64     := 32;
    C_NUMBER_OF_PC_BRK      : natural range 0 to 15     := 1;
    C_NUMBER_OF_RD_ADDR_BRK : natural range 0 to 7      := 0;
    C_NUMBER_OF_WR_ADDR_BRK : natural range 0 to 7      := 0
    );
  port (
    -- JTAG_UART signals
    TClk    : in  std_logic;
    TDI     : in  std_logic;
    TDO     : out std_logic;
    Reg_En  : in  std_logic_vector(0 to 4);
    Shift   : in  std_logic;
    Capture : in  std_logic;            -- Read
    Update  : in  std_logic;            -- Write

    -- MicroBlaze signals
    Clk      : in std_logic;
    Reset    : in boolean;
    Dbg_Stop : in std_logic;

    Use_Imm_Reg       : in boolean;
    Branch_with_delay : in boolean;
    Delay_Slot_Instr  : out std_logic;

    -- Needed for the Breakpoint
    PC_OF      : in std_logic_vector(0 to C_DATA_SIZE-1);
    OF_PipeRun : in boolean;

    -- Registers to read
    PC_EX       : in std_logic_vector(0 to C_DATA_SIZE-1);
    Valid_Instr : in std_logic;
    MSR         : in MSR_REG_TYPE;

    -- Signals needed for Read/Write to memory
    Reg_Write     : in std_logic;
    New_Reg_Value : in std_logic_vector(0 to C_DATA_SIZE-1);

    Debug_Ready      : out std_logic;
    Instr_Debug      : out std_logic_vector(0 to 31);
    Stop_Instr_Fetch : out std_logic;

    -- Signals needed for Memory breakpoints
    Data_Addr   : in std_logic_vector(0 to C_DATA_SIZE-1);
    Data_Write  : in std_logic_vector(0 to C_DATA_SIZE-1);
    Write_Instr : in std_logic;
    Read_Instr  : in std_logic;
    DReady      : in std_logic;

    -- MicroBlaze stalling conditions
    FSL_Stalled    : in std_logic;
    Memory_Stalled : in std_logic;
    
    -- Stop MicroBlaze
    Ok_To_Stop            : in  std_logic;  -- Ok to stop the CPU ie. No BRK or
                                            -- Interrupts and a valid instruction
                                            -- in OF stage
    Dbg_Inhibit_EX        : out std_logic;
    Stop_CPU              : out std_logic;
    Dbg_Disable_Interrupt : out boolean;

    MB_Halted : out std_logic;

    -- Debug signals for debugging debug logic!!!!
    Control_Reg_D : out std_logic_vector(0 to 3);
    Command_Reg_D : out std_logic_vector(0 to 7)

    );
end entity Debug;

library unisim;
use unisim.vcomponents.all;

library IEEE;
use IEEE.numeric_std.all;

architecture IMP of Debug is

  component address_hit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      C_FIRST  : boolean            := false;
      No_Bits  : natural);
    port (
      Address       : in  std_logic_vector(0 to No_Bits-1);
      Armed         : in  std_logic;
      TClk          : in  std_logic;
      TDI           : in  std_logic;
      SRL16_En      : in  std_logic;
      Single_Step_N : in  std_logic;
      Hit           : out std_logic);
  end component address_hit;
  
  component address_data_hit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      No_Bits  : natural);
    port (
      Address  : in  std_logic_vector(0 to No_Bits-1);
      Data     : in  std_logic_vector(0 to No_Bits-1);
      Armed    : in  std_logic;
      TClk     : in  std_logic;
      TDI      : in  std_logic;
      SRL16_En : in  std_logic;
      Hit      : out std_logic);
  end component address_data_hit;
  
  function int2std (val : integer) return std_logic is
  begin  -- function int2std
    if (val = 0) then
      return '0';
    else
      return '1';
    end if;
  end function int2std;

  constant PC_BRKS       : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(C_NUMBER_OF_PC_BRK, 4));
  constant RD_ADDR_BRK_I : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_NUMBER_OF_RD_ADDR_BRK, 3));
  constant WR_ADDR_BRK_I : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_NUMBER_OF_WR_ADDR_BRK, 3));
  constant VERSION_I     : std_logic_vector(3 downto 0) := "1110"; -- Denotes that Config_Init_Word4 has version info

  constant Using_I_Cache : std_logic := int2std(C_USE_ICACHE);
  constant Using_D_Cache : std_logic := int2std(C_USE_DCACHE);

  constant Config_Init_Word : std_logic_vector(15 downto 0) := Using_I_Cache & RD_ADDR_BRK_I &
                                                               Using_D_Cache & WR_ADDR_BRK_I &
                                                               PC_BRKS &
                                                               VERSION_I;

  constant No_FSLs : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(C_FSL_LINKS, 6));
  constant Has_FPU  : std_logic                    := int2std(C_USE_FPU);
  constant Has_Exceptions : std_logic := int2std(C_UNALIGNED_EXCEPTIONS + C_ILL_OPCODE_EXCEPTION +
                                                 C_IOPB_BUS_EXCEPTION   + C_DOPB_BUS_EXCEPTION   +
                                                 C_IPLB_BUS_EXCEPTION   + C_DPLB_BUS_EXCEPTION   +
                                                 C_DIV_ZERO_EXCEPTION   + C_FPU_EXCEPTION        +
                                                 C_FSL_EXCEPTION * C_USE_EXTENDED_FSL_INSTR * C_FSL_LINKS);
  constant Has_DIV        : std_logic := int2std(C_USE_DIV);
  constant Has_HW_MUL     : std_logic := int2std(C_USE_HW_MUL);
  constant Has_Barrel     : std_logic := int2std(C_USE_BARREL);
  constant Has_MSR_Instr  : std_logic := int2std(C_USE_MSR_INSTR);
  constant Has_PCMP_Instr : std_logic := int2std(C_USE_PCMP_INSTR);
  constant Has_FSL_ICache : std_logic := int2std(C_ICACHE_USE_FSL);
  constant Has_FSL_DCache : std_logic := int2std(C_DCACHE_USE_FSL);

  constant Config_Init_Word2 : std_logic_vector(15 downto 0) := No_FSLs & Has_HW_MUL & Has_FPU & Has_Exceptions & Has_DIV &
                                                                Has_Barrel & Has_MSR_Instr & Has_PCMP_Instr & Has_FSL_ICache &
                                                                Has_FSL_DCache & '0';
    
  constant Has_PVR       : std_logic := int2std(C_PVR);
  constant Has_Full_PVR  : std_logic := int2std(C_PVR/2);
  constant Has_Mul64     : std_logic := int2std(C_USE_HW_MUL/2);
  constant Optimize_Area : std_logic := '1';
  constant Interconnect  : std_logic := int2std(C_INTERCONNECT);
  constant Has_FPU2      : std_logic := int2std(C_USE_FPU/2);

  constant Config_Init_Word3 : std_logic_vector(15 downto 0) := Has_PVR & Has_Full_PVR & Has_Mul64 & Optimize_Area & Interconnect & Has_FPU2 & "0000000000";
  constant Config_Init_Word4 : std_logic_vector(15 downto 0) := C_MB_VERSION & C_PVR_USER1;

  -- Optional configuration information based on MB PVR register
  constant Config_Init_Word5 : std_logic_vector(15 downto 0) := C_PVR_USER2(0 to 15);
  constant Config_Init_Word6 : std_logic_vector(15 downto 0) := C_PVR_USER2(16 to 31);

  constant Cache_Init_Word : std_logic_vector(127 downto 0) := C_ICACHE_BASEADDR & C_ICACHE_HIGHADDR & C_DCACHE_BASEADDR & C_DCACHE_HIGHADDR;

  -- only positive values
  function itohex (int : natural; len : natural) return string is
    type     table is array (0 to 15) of character;
    constant LUT : table :=
      ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F');
    variable str        : string(1 to len);
    variable rest, temp : natural;
  begin
    temp := int;
    for I in Len downto 1 loop
      rest   := temp mod 16;
      temp   := temp / 16;
      str(I) := LUT(rest);
    end loop;  -- I
    return str;
  end function itohex;


  function calc_brks return natural is
    variable t : natural;
  begin  -- function calc_brks
    t := C_NUMBER_OF_PC_BRK + C_NUMBER_OF_WR_ADDR_BRK + C_NUMBER_OF_RD_ADDR_BRK;
    if (C_NUMBER_OF_PC_BRK = 0) then
      t := t + 1;                       -- Need one extra for single stepping
    end if;
    return t;
  end function calc_brks;

  constant C_NR_OF_BRKS : natural := calc_brks;

  signal TDO_Status_Reg  : std_logic;
  signal TDO_Data_Reg    : std_logic;
  signal TDO_Config_Word : std_logic;

  signal Config_Reg_En           : std_logic;
  signal Control_Reg_En          : std_logic;
  signal Status_Reg_En           : std_logic;
  signal Command_Reg_En          : std_logic;
  signal Instr_Insert_Reg_En     : std_logic;
  signal Instr_Insert_Reg_En_1   : std_logic := '0';
  signal Instr_Insert_Reg_En_Clk : std_logic;
  signal Data_Read_Reg_En        : std_logic;

  -----------------------------------------------------------------------------
  -- CPU control signals
  -----------------------------------------------------------------------------

  signal free_running : std_logic;

  signal control_reg : std_logic_vector(0 to 5) := "000000";
  -- Bit 0  Armed
  -- Bit 1  Single Step
  -- Bit 2  Continue from breakpoint
  -- Bit 3  Disable Interrupts
  -- Bit 4  Single_Step_Count bit 0
  -- Bit 5  Single_Step_Count bit 1

  constant single_step_pos_C  : natural := 1;
  constant continue_pos_C     : natural := 2;
  constant dis_intr_pos_C     : natural := 3;
  constant single_value_pos_C : natural := 4;

  signal single_Step_TClk       : std_logic := '0';
  signal continue_from_brk_TClk : std_logic := '0';