debug_gti.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: debug_gti.vhd,v 1.2 2007/12/13 13:56:42 stefana Exp $
-------------------------------------------------------------------------------
-- debug.vhd
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** Copyright(C) 2001-2005 by Xilinx, Inc. All rights reserved.
-- **
-- ** This text contains proprietary, confidential information of
-- ** Xilinx, Inc. , is distributed by under license from Xilinx, Inc.,
-- ** and may be used, copied and/or disclosed only pursuant to the
-- ** terms of a valid license agreement with Xilinx, Inc.
-- **
-- ** Unmodified source code is guaranteed to place and route,
-- ** function and run at speed according to the datasheet
-- ** specification. Source code is provided "as-is", with no
-- ** obligation on the part of Xilinx to provide support.
-- **
-- ** Xilinx Hotline support of source code IP shall only include
-- ** standard level Xilinx Hotline support, and will only address
-- ** issues and questions related to the standard released Netlist
-- ** version of the core (and thus indirectly, the original core source
-- **
-- ** The Xilinx Support Hotline does not have access to source
-- ** code and therefore cannot answer specific questions related
-- ** to source HDL. The Xilinx Support Hotline will only be able
-- ** to confirm the problem in the Netlist version of the core.
-- **
-- ** This copyright and support notice must be retained as part
-- ** of this text at all times.
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        debug.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93
-------------------------------------------------------------------------------
-- Structure:   
--              debug.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.2 $
-- Date:            $Date: 2007/12/13 13:56:42 $
--
-- History:
--   goran  2002-03-21    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "*_clk"
--      reset signals:                          "rst", "*_rst", "reset"
--      generics:                               All uppercase, starting with: "C_"
--      constants:                              All uppercase, not starting with: "C_"
--      state machine next state:               "*_next_state"
--      state machine current state:            "*_curr_state"
--      pipelined signals:                      "*_d#"
--      counter signals:                        "*_cnt_*" , "*_counter_*", "*_count_*"
--      internal version of output port:        "*_i"
--      ports:                                  Names begin with uppercase
--      component instantiations:               "<ENTITY>_I#|<FUNC>" , "<ENTITY>_I"
--
-- Signals starting with IF, OF, EX, MEM, or WB indicate that they start in that
-- stage:
--
--    IF                                -- instruction fetch
--    OF                                -- operand fetch
--    EX                                -- execute
--    MEM                               -- memory
--    WB                                -- write back
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity Debug_gti is
  generic (
    C_USE_BARREL           : integer := 0;
    C_USE_DIV              : integer := 0;
    C_USE_HW_MUL           : integer := 0;
    C_USE_FPU              : integer := 0;
    C_USE_MSR_INSTR        : integer := 0;
    C_USE_PCMP_INSTR       : integer := 0;
    C_UNALIGNED_EXCEPTIONS : integer := 0;
    C_ILL_OPCODE_EXCEPTION : integer := 0;
    C_IOPB_BUS_EXCEPTION   : integer := 0;
    C_DOPB_BUS_EXCEPTION   : integer := 0;
    C_IPLB_BUS_EXCEPTION   : integer := 0;
    C_DPLB_BUS_EXCEPTION   : integer := 0;
    C_DIV_ZERO_EXCEPTION   : integer := 0;
    C_FPU_EXCEPTION        : integer := 0;
    C_FSL_EXCEPTION        : integer := 0;
    C_FSL_LINKS            : integer := 0;
    C_USE_EXTENDED_FSL_INSTR  : integer := 0;
    C_PVR                  : integer := 0;
    C_PVR_USER1            : std_logic_vector(0 to 7);
    C_PVR_USER2            : std_logic_vector(0 to 31);
    C_MB_VERSION           : std_logic_vector(0 to 7);
    C_INTERCONNECT         : integer := 0;

    C_USE_ICACHE            : integer                   := 0;
    C_ICACHE_USE_FSL        : integer                   := 0;
    C_ICACHE_BASEADDR       : std_logic_vector(0 to 31) := X"00000000";
    C_ICACHE_HIGHADDR       : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_USE_DCACHE            : integer                   := 0;
    C_DCACHE_USE_FSL        : integer                   := 0;
    C_DCACHE_BASEADDR       : std_logic_vector(0 to 31) := X"00000000";
    C_DCACHE_HIGHADDR       : std_logic_vector(0 to 31) := X"3FFFFFFF";
    C_TARGET                : TARGET_FAMILY_TYPE;
    C_DATA_SIZE             : natural range 4 to 64     := 32;
    C_NUMBER_OF_PC_BRK      : natural range 0 to 15     := 1;
    C_NUMBER_OF_RD_ADDR_BRK : natural range 0 to 7      := 0;
    C_NUMBER_OF_WR_ADDR_BRK : natural range 0 to 7      := 0;
    C_USE_MMU               : integer;
    C_MMU_DTLB_SIZE         : integer;
    C_MMU_ITLB_SIZE         : integer;
    C_MMU_TLB_ACCESS        : integer;
    C_MMU_ZONES             : integer
    );
  port (
    -- JTAG_UART signals
    TClk    : in  std_logic;
    TDI     : in  std_logic;
    TDO     : out std_logic;
    Reg_En  : in  std_logic_vector(0 to 4);
    Shift   : in  std_logic;
    Capture : in  std_logic;            -- Read
    Update  : in  std_logic;            -- Write

    -- MicroBlaze signals
    Clk      : in std_logic;
    Reset    : in std_logic;
    Dbg_Stop : in std_logic;

    OF_Valid_Instr     : in  boolean;
    WB_DelaySlot_Instr : in  boolean;
    WB_Read_Imm_Reg    : in  boolean;
    WB_Read_Imm_Reg_1  : in  boolean;

    -- Needed for the Breakpoint
    PC_OF      : in std_logic_vector(0 to C_DATA_SIZE-1);
    OF_PipeRun : in boolean;
    EX_PipeRun : in boolean;
    MEM_PipeRun : in boolean;
    WB_PipeRun  : in boolean;

    -- Debug control signals
    Dbg_Disable_Interrupt   : out boolean;
    
    -- Registers to read
    WB_PC          : in std_logic_vector(0 to C_DATA_SIZE-1);
    WB_PC_Valid    : in std_logic;
    WB_MSR         : in MSR_TYPE;

    -- Signals needed latching write data to the register file
    WB_GPR_Wr_Dbg : in boolean;
    WB_Fwd        : in std_logic_vector(0 to C_DATA_SIZE-1);  -- WB_Fwd

    -- Signals needed for inserting instructions into the prefetch buffer
    IF_Debug_Ready       : out std_logic;
    IF_Debug_Instr       : out std_logic_vector(0 to 31);
    Dbg_Stop_Instr_Fetch : out std_logic;

    -- Signals needed for detecting Memory breakpoints
    MEM_Data_Addr                : in std_logic_vector(0 to C_DATA_SIZE-1);
    MEM_Data_Write               : in std_logic_vector(0 to C_DATA_SIZE-1);
    MEM_Write_Instr              : in std_logic;
    MEM_Read_Instr               : in std_logic;
    MEM_DReady                   : in std_logic;
    WB_DataBus_Steered_Read_Data : in DATA_TYPE;  -- WB read from databus result

    -- MicroBlaze stalling conditions
    FSL_Stalled    : in std_logic;
    Memory_Stalled : in std_logic;
    
    -- Stop MicroBlaze
    EX_Dbg_PC_Hit            : out boolean;  -- PC Breakpoint
    EX_Exception_Taken       : in  boolean;

    Dbg_Freeze : out boolean;           -- Freeze Pipeline
    Dbg_State  : out boolean;           -- MicroBlaze in Dbg_state
    
    -- A debug condition has reached WB and MicroBlaze is halted
    WB_Halted : in boolean

    );
end entity Debug_gti;

-- pragma xilinx_rtl_off
library unisim;
use unisim.all;
-- pragma xilinx_rtl_on

library IEEE;
use IEEE.numeric_std.all;

architecture IMP of Debug_gti is

  component address_hit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      C_FIRST  : boolean := false;
      No_Bits  : natural);
    port (
      Address       : in  std_logic_vector(0 to No_Bits-1);
      Armed         : in  std_logic;
      TClk          : in  std_logic;
      TDI           : in  std_logic;
      SRL16_En      : in  std_logic;
      Single_Step_N : in  std_logic;
      Hit           : out std_logic);
  end component address_hit;

  component address_data_hit is
    generic (
      C_TARGET : TARGET_FAMILY_TYPE;
      No_Bits  : natural);
    port (
      Address  : in  std_logic_vector(0 to No_Bits-1);
      Data     : in  std_logic_vector(0 to No_Bits-1);
      Armed    : in  std_logic;
      TClk     : in  std_logic;
      TDI      : in  std_logic;
      SRL16_En : in  std_logic;
      Hit      : out std_logic);
  end component address_data_hit;

  -- pragma xilinx_rtl_off

  attribute BOX_TYPE : string;

  component FDRSE is
    generic(
      INIT : bit := '0'
      );
    port (
      Q  : out std_logic;
      C  : in  std_logic;
      CE : in  std_logic;
      D  : in  std_logic;
      R  : in  std_logic;
      S  : in  std_logic);
  end component FDRSE;

  attribute BOX_TYPE of FDRSE : component is "black_box";

  component SRL16E is
    generic (
      INIT : bit_vector(15 downto 0)
      );
    port (
      CE  : in  std_logic;
      D   : in  std_logic;
      Clk : in  std_logic;
      A0  : in  std_logic;
      A1  : in  std_logic;
      A2  : in  std_logic;
      A3  : in  std_logic;
      Q   : out std_logic);
  end component SRL16E;

  attribute BOX_TYPE of SRL16E : component is "black_box";

  -- pragma xilinx_rtl_on

  function int2std (val : integer) return std_logic is
  begin  -- function int2std
    if (val = 0) then
      return '0';
    else
      return '1';
    end if;
  end function int2std;

  constant PC_BRKS       : std_logic_vector(3 downto 0) := std_logic_vector(to_unsigned(C_NUMBER_OF_PC_BRK, 4));
  constant RD_ADDR_BRK_I : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_NUMBER_OF_RD_ADDR_BRK, 3));
  constant WR_ADDR_BRK_I : std_logic_vector(2 downto 0) := std_logic_vector(to_unsigned(C_NUMBER_OF_WR_ADDR_BRK, 3));
  constant VERSION_I     : std_logic_vector(3 downto 0) := "1110"; -- Denotes that Config_Init_Word4 has version info

  constant Using_I_Cache : std_logic := int2std(C_USE_ICACHE);
  constant Using_D_Cache : std_logic := int2std(C_USE_DCACHE);

  constant Config_Init_Word : std_logic_vector(15 downto 0) := Using_I_Cache & RD_ADDR_BRK_I &
                                                               Using_D_Cache & WR_ADDR_BRK_I &
                                                               PC_BRKS &
                                                               VERSION_I;

  constant No_FSLs : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(C_FSL_LINKS, 6));
  constant Has_FPU : std_logic                    := int2std(C_USE_FPU);
  constant Has_Exceptions : std_logic := int2std(C_UNALIGNED_EXCEPTIONS + C_ILL_OPCODE_EXCEPTION +
                                                 C_IOPB_BUS_EXCEPTION   + C_DOPB_BUS_EXCEPTION   +
                                                 C_IPLB_BUS_EXCEPTION   + C_DPLB_BUS_EXCEPTION   +
                                                 C_DIV_ZERO_EXCEPTION   + C_FPU_EXCEPTION        +
                                                 C_FSL_EXCEPTION * C_USE_EXTENDED_FSL_INSTR * C_FSL_LINKS +
                                                 C_USE_MMU);
  constant Has_DIV        : std_logic := int2std(C_USE_DIV);
  constant Has_HW_MUL     : std_logic := int2std(BOOLEAN'POS(C_USE_HW_MUL = 1));
  constant Has_Barrel     : std_logic := int2std(C_USE_BARREL);
  constant Has_MSR_Instr  : std_logic := int2std(C_USE_MSR_INSTR);
  constant Has_PCMP_Instr : std_logic := int2std(C_USE_PCMP_INSTR);
  constant Has_FSL_ICache : std_logic := int2std(C_ICACHE_USE_FSL);
  constant Has_FSL_DCache : std_logic := int2std(C_DCACHE_USE_FSL);
  constant Has_MMU        : std_logic_vector(1 downto 0) := std_logic_vector(to_unsigned(C_USE_MMU, 2));

  constant Config_Init_Word2 : std_logic_vector(15 downto 0) := No_FSLs & Has_HW_MUL & Has_FPU & Has_Exceptions & Has_DIV &
                                                                Has_Barrel & Has_MSR_Instr & Has_PCMP_Instr & Has_FSL_ICache &
                                                                Has_FSL_DCache & '0';
  
  constant Has_PVR       : std_logic := int2std(C_PVR);
  constant Has_Full_PVR  : std_logic := int2std(C_PVR/2);
  constant Has_Mul64     : std_logic := int2std(C_USE_HW_MUL/2);
  constant Optimize_Area : std_logic := '0';
  constant Interconnect  : std_logic := int2std(C_INTERCONNECT);
  constant Has_FPU2      : std_logic := int2std(C_USE_FPU/2);

  constant Config_Init_Word3 : std_logic_vector(15 downto 0) := Has_PVR & Has_Full_PVR & Has_Mul64 & Optimize_Area &
                                                                Interconnect & Has_FPU2 & Has_MMU & "00000000";
  constant Config_Init_Word4 : std_logic_vector(15 downto 0) := C_MB_VERSION & C_PVR_USER1;

  -- Optional configuration information based on MB PVR register
  constant Config_Init_Word5 : std_logic_vector(15 downto 0) := C_PVR_USER2(0 to 15);
  constant Config_Init_Word6 : std_logic_vector(15 downto 0) := C_PVR_USER2(16 to 31);

  constant Cache_Init_Word : std_logic_vector(127 downto 0) := C_ICACHE_BASEADDR & C_ICACHE_HIGHADDR & C_DCACHE_BASEADDR & C_DCACHE_HIGHADDR;

  -- only positive values
  function itohex (int : natural; len : natural) return string is
    type     table is array (0 to 15) of character;
    constant LUT : table :=
      ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F');
    variable str        : string(1 to len);
    variable rest, temp : natural;
  begin
    temp := int;
    for I in Len downto 1 loop