fpu_conv.vhd

Xilinx软核microblaze源码(VHDL)版本7.10

-------------------------------------------------------------------------------
-- $Id: fpu_conv.vhd,v 1.1 2007/10/12 09:11:36 stefana Exp $
-------------------------------------------------------------------------------
-- fpu_conv.vhd - Entity and architecture
--
--  ***************************************************************************
--  **  Copyright(C) 2003 by Xilinx, Inc. All rights reserved.               **
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--  **  Unmodified source code is guaranteed to place and route,             **
--  **  function and run at speed according to the datasheet                 **
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--  **  obligation on the part of Xilinx to provide support.                 **
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--  **  Xilinx Hotline support of source code IP shall only include          **
--  **  standard level Xilinx Hotline support, and will only address         **
--  **  issues and questions related to the standard released Netlist        **
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--  **  This copyright and support notice must be retained as part           **
--  **  of this text at all times.                                           **
--  ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename:        fpu_conv.vhd
--
-- Description:     
--                  
-- VHDL-Standard:   VHDL'93/02
-------------------------------------------------------------------------------
-- Structure:   
--              fpu_conv.vhd
--
-------------------------------------------------------------------------------
-- Author:          goran
-- Revision:        $Revision: 1.1 $
-- Date:            $Date: 2007/10/12 09:11:36 $
--
-- History:
--   goran  2006-11-28    First Version
--
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x" 
--      reset signals:                          "rst", "rst_n" 
--      generics:                               "C_*" 
--      user defined types:                     "*_TYPE" 
--      state machine next state:               "*_ns" 
--      state machine current state:            "*_cs" 
--      combinatorial signals:                  "*_com" 
--      pipelined or register delay signals:    "*_d#" 
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce" 
--      internal version of output port         "*_i"
--      device pins:                            "*_pin" 
--      ports:                                  - Names begin with Uppercase 
--      processes:                              "*_PROCESS" 
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library Microblaze_v7_10_a;
use Microblaze_v7_10_a.MicroBlaze_ISA.all;
use Microblaze_v7_10_a.MicroBlaze_Types.all;

entity fpu_conv is
  port (
    Clk                : in  std_logic;
    Reset              : in  std_logic;
    EX_PipeRun         : in  boolean;
    EX_Op1             : in  DATA_TYPE;
    EX_Op1_Mant_Zero   : in  boolean;
    EX_Flt_Op          : in  boolean;
    EX_Int_Op          : in  boolean;
    EX_Start_Fpu       : in  boolean;
    MEM_Flt_Done       : out boolean;
    MEM_Flt_Result_4   : out FPU_MANT_IGRS_TYPE;
    MEM_Flt_Exp_4      : out FPU_EXP_TYPE;
    MEM_Int_Done_Early : out boolean;
    MEM_Int_Done       : out boolean;
    Mem_Int_Zero_3     : out boolean;
    Mem_Int_Inv_3      : out boolean;
    MEM_Int_Result_5   : out DATA_TYPE
    );
end entity fpu_conv;

library unisim;
use unisim.vcomponents.all;

architecture IMP of fpu_conv is

  signal fconv_sign_1 : std_logic;
  signal fconv_sign_2 : std_logic;
  signal fconv_sign_3 : std_logic;

  signal fconv_op_1         : std_logic_vector(0 to 31);
  signal fconv_op_2         : std_logic_vector(0 to 33);
  signal fconv_op_3_shifted : std_logic_vector(0 to 33);
  signal fconv_op_3         : std_logic_vector(0 to 31);

  signal fsb_i     : natural range 0 to 31;
  signal flt_fsb_2 : natural range 0 to 31;

  signal left_shifting : boolean;
  signal shift         : std_logic_vector(0 to 4);

  signal int_op_1 : boolean;
  signal int_op_2 : boolean;
  signal int_op_3 : boolean;

  signal flt_op_1 : boolean;
  signal flt_op_2 : boolean;
  signal flt_op_3 : boolean;
  signal flt_op_4 : boolean;

  signal flt_grs_3 : std_logic_vector(0 to 2);
  signal flt_exp_3 : FPU_EXP_TYPE;

  subtype special_res_type is std_logic_vector(0 to 1);
  constant Normal          : special_res_type := "00";
  constant Max_Int         : special_res_type := "01";
  constant Zero            : special_res_type := "10";
  signal int_special_res_1 : special_res_type;
  signal int_special_res_2 : special_res_type;
  signal int_special_res_3 : special_res_type;
  signal fconv_op1_abs     : std_logic_vector(0 to 31);

  constant int_special_res_max_neg : std_logic_vector(0 to 31) := X"80000000";
  constant int_special_res_zero    : std_logic_vector(0 to 31) := X"00000000";

  signal int_res_alu : std_logic_vector(0 to 31);

begin  -- architecture IMP

  ---------------------------------------------------------------------------
  -- Need to find FSB set on a absolute value  
  ---------------------------------------------------------------------------
  abs_op1 : block is
    signal fconv_op1_invert    : std_logic;
    signal fconv_op1_abs_carry : std_logic_vector(0 to 32);
    signal fconv_op1_abs_sel   : std_logic_vector(0 to 31);
  begin  -- block abs_op1
    -----------------------------------------------------------------------------
    -- Do a conditional ABS of the operand
    -----------------------------------------------------------------------------
    fconv_op1_invert        <= EX_Op1(0) when EX_Flt_Op else '0';
    fconv_op1_abs_carry(32) <= fconv_op1_invert;

    fconv_op1_abs_GEN : for I in 31 downto 0 generate
      fconv_op1_abs_sel(I) <= not(EX_Op1(I)) when fconv_op1_invert = '1'
                              else EX_Op1(I);
      fconv_op1_abs_MUXCY_L : MUXCY_L
        port map (
          DI => '0',                       -- [in  std_logic]
          CI => fconv_op1_abs_carry(I+1),  -- [in  std_logic]
          S  => fconv_op1_abs_sel(I),      -- [in  std_logic]
          LO => fconv_op1_abs_carry(I));   -- [out std_logic]

      fconv_op1_abs_XORCY : XORCY
        port map (
          LI => fconv_op1_abs_sel(I),      -- [in  std_logic]
          CI => fconv_op1_abs_carry(I+1),  -- [in  std_logic]
          O  => fconv_op1_abs(I));         -- [out std_logic]    
    end generate fconv_op1_abs_GEN;
  end block abs_op1;

  Op1_DFF : process(Clk) is
  begin  -- process Op1_DFF
    if Clk'event and Clk = '1' then
      if Reset = '1' then
        fconv_op_1 <= (others => '0');
      elsif EX_PipeRun then
        fconv_op_1 <= fconv_op1_abs;
      end if;
    end if;
  end process Op1_DFF;

  Stage1_Ctrl : process(Clk) is
  begin  -- process Stage1_Ctrl
    if Clk'event and Clk = '1' then
      if Reset = '1' then
        fconv_sign_1      <= '0';
        Mem_Int_Zero_3    <= false;
        Mem_Int_Inv_3     <= false;
        int_special_res_1 <= Normal;
        int_op_1          <= false;
        flt_op_1          <= false;
      else
        int_op_1 <= EX_PipeRun and EX_Start_Fpu and EX_Int_Op;
        flt_op_1 <= EX_PipeRun and EX_Start_Fpu and EX_Flt_Op;
        if EX_PipeRun and EX_Start_Fpu then
          fconv_sign_1 <= '0';
          if (EX_Int_Op) then
            fconv_sign_1 <= ex_op1(IEEE754_SINGLE_SIGN_POS);
          end if;
          Mem_Int_Zero_3    <= false;
          Mem_Int_Inv_3     <= false;
          int_special_res_1 <= Normal;
          if (EX_Int_Op) then
--          if (unsigned(EX_Op1(1 to 8)) < 127) then
            if ((EX_Op1(1) = '0') and (EX_Op1(2 to 8) /= "1111111")) then
              Mem_Int_Zero_3    <= true;
              int_special_res_1 <= Zero;
            end if;
            if (unsigned(EX_Op1(1 to 8)) >= 158) then
              if ((Ex_Op1(0) = '1') and (EX_Op1(1 to 8) = "10011110") and EX_Op1_Mant_Zero) then
                int_special_res_1 <= Max_Int;
              else
                Mem_Int_Inv_3 <= true;
              end if;
            end if;
          end if;
        end if;
      end if;
    end if;
  end process Stage1_Ctrl;

  ---------------------------------------------------------------------------
  -- Need to find the first bit set
  ---------------------------------------------------------------------------
  process(fconv_op_1) is
    variable fsb_temp : natural range 0 to 31;
  begin
    fsb_temp := 0;
    for I in 0 to 31 loop
      if fconv_op_1(I) = '1' then
        fsb_temp := I;
        exit;
      end if;
    end loop;
    fsb_i <= fsb_temp;
  end process;

  FCONV_FSB_PROC : process (Clk) is
    variable temp_exp   : std_logic_vector(0 to 8);
    variable temp_shift : std_logic_vector(1 to 8);                                 
  begin  -- process FCONV_FSB_PROC
    if Clk'event and Clk = '1' then     -- rising clock edge
      if Reset = '1' then               -- synchronous reset (active high)
        flt_fsb_2         <= 0;
        fconv_sign_2      <= '0';
        shift             <= (others => '0');
        left_shifting     <= false;
        int_op_2          <= false;
        flt_op_2          <= false;
        int_special_res_2 <= Normal;
        fconv_op_2        <= (others => '0');
      else
        fconv_op_2        <= fconv_op_1 & "00";
        fconv_sign_2      <= fconv_sign_1;
        int_op_2          <= int_op_1;
        flt_op_2          <= flt_op_1;
        int_special_res_2 <= int_special_res_1;
        flt_fsb_2         <= fsb_i;
        temp_exp          := std_logic_vector(unsigned('0' & fconv_op_1(1 to 8)) - 150);
        if (flt_op_1) then
          if (fsb_i >= 8) then
            shift         <= std_logic_vector(to_unsigned(fsb_i-8,5));
            left_shifting <= true;
          else
            shift         <= std_logic_vector(to_unsigned(8-fsb_i,5));
            left_shifting <= false;
          end if;
        else
          fconv_op_2(0 to 8) <= "00000000" & '1';
          if (temp_exp(0) = '1') then   -- less than 151
            left_shifting <= false;
--            shift      <= (150 - to_integer(unsigned(fconv_op_1(1 to 8)))) mod 32;