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Logic Analyzer 的代码
pcit_core.vhd
--*****************************************************************************
-- DESIGN : PCI Target Core
-- FILE : PCIT_CORE.vhd
-- DATE : 1.9.1999
-- REVISION: 1.1
-- DESIGNER: KA
--
ball.vhd
--乒乓球灯模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ball is
port(clk:in std_logic;--乒乓球灯前进时钟
clr:in std_logic;--乒乓球灯清零
way:in std_logic;--乒乓球灯前进方向
en
cnt24.vhd
LIBRARY IEEE; -- 24进制计数器
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT24 IS
PORT ( CLK,EN, U_D : IN STD_LOGIC;
planeagc.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
openlock.vhd
library ieee;
use ieee.std_logic_1164.all;
entity openlock is
port( clk : in std_logic;
change : in std_logic;
test : in std_logic;
code0 : in std_logic_vector(3 downto 0);
bcdconvtb.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
entity BCDConvTB is
end;
architecture Bench of BCDConvTB is
bcdconv.vhd
--
-- Copyright (C) Doulos Ltd 2001
--
library IEEE;
use IEEE.std_logic_1164.all;
entity BCDConv is
generic (N : positive); -- number of digits
port (Clock : in std_logic;
a.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity a is port(
);
read.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity read is port(
clk,rst,lint2,wrfull: in std_logic;
ads,blast,wr,waitt,wrreq:out std_logic;
ready : in st
int.vhd.bak
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity int is port(
lint : in std_logic;
clk,rst : in std_logic;
lint1,lint2 : b