openlock.vhd

电子密码锁

library ieee;
use ieee.std_logic_1164.all;
entity openlock is
port( clk : in std_logic;
      change : in std_logic;
      test : in std_logic;
      code0 : in std_logic_vector(3 downto 0);
      code1 : in std_logic_vector(3 downto 0);
      code2 : in std_logic_vector(3 downto 0);
      code3 : in std_logic_vector(3 downto 0);
      code4 : in std_logic_vector(3 downto 0);
      code5 : in std_logic_vector(3 downto 0);
      lockopen : out std_logic;
      lockclose : out std_logic);
end entity;
architecture behav of openlock is
signal enable,enable1 : std_logic;
signal temp0,temp1,temp2,temp3,temp4,temp5 : std_logic_vector(3 downto 0);
begin
  enable<=change and (not test);
  enable1<=test and (not change);
  process(clk,code0,code1,code2,code3,code4,code5,change,test)
  begin
    if rising_edge(clk) then
      if enable='1' then
        temp0<=code0;
        temp1<=code1;
        temp2<=code2;
        temp3<=code3;
        temp4<=code4;
        temp5<=code5;
      end if;
      if enable1='1' then
        if temp0=code0 and temp1=code1 and temp2=code2 and temp3=code3 and temp4=code4 and temp5=code5 then
          lockopen<='1';
          lockclose<='0';
        else
          lockopen<='0';
          lockclose<='1';  
        end if;
      end if;
    end if;
  end process;
end behav;