planeagc.vhd

AGC的vhdl实现

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity planeAgc is
port   (Rst				:in std_logic;
		Clk				:in std_logic;
		DataIn			:in std_logic_vector(15 downto 0);
		IntegralLength	:in std_logic_vector(15 downto 0);
		Ref				:in std_logic_vector(15 downto 0);	
		C0				:in std_logic_vector(15 downto 0);
		Clear			:in std_logic;	
		Obdata			:out std_logic_vector(15 downto 0);	
		VagBuf			:out std_logic_vector(15 downto 0);
		VagEn			:out std_logic);						
end planeAgc;

architecture Behavioral of planeAgc is

signal Load				:std_logic;
signal MulSumOut		:std_logic_vector (47 downto 0);
signal Cnt				:std_logic_vector(15 downto 0);
signal AdjustData		:std_logic_vector(15 downto 0);
signal Cemp				:std_logic;
signal VagBufTemp		:std_logic_vector (47 downto 0);

COMPONENT AGCPowSum
   port ( A_IN    : in    std_logic_vector (15 downto 0); 
          B_IN    : in    std_logic_vector (15 downto 0); 
          CEM_IN  : in    std_logic; 
          CEP_IN  : in    std_logic; 
          CLK_IN  : in    std_logic; 
          LOAD_IN : in    std_logic; 
          RSTM_IN : in    std_logic; 
          RSTP_IN : in    std_logic; 
          P_OUT   : out   std_logic_vector (47 downto 0));
end component;

begin

Obdata <= MulSumOut(47 downto 32);
AdjustData <= Ref -	MulSumOut(47 downto 32);
Cemp <= not Load;
VagBuf <= VagBufTemp(47 downto 32);

Inst_AGCPowSum1: AGCPowSum PORT MAP(
	A_IN => DataIn,
	B_IN => DataIn,
    CEM_IN =>'1', 
    CEP_IN =>'1',
	CLK_IN => Clk,
	LOAD_IN => Load,
	RSTM_IN => Rst,
	RSTP_IN => Rst,
	P_OUT => MulSumOut
);

Inst_AGCPowSum2: AGCPowSum PORT MAP(
	A_IN => C0,
	B_IN => AdjustData,
    CEM_IN =>Cemp, 
    CEP_IN =>Cemp,
	CLK_IN => Clk,
	LOAD_IN => Clear,
	RSTM_IN => Rst,
	RSTP_IN => Rst,
	P_OUT => VagBufTemp
);
process(Rst,Clk)
begin
	if Rst ='1' then
		Cnt	<= (others =>'0');
		Load <= '1';
		vagen <='0';
	elsif Clk'event and Clk='1' then
		VagEn <= Cemp;
		if 	Cnt >= IntegralLength then
			Cnt	<= (others =>'0');
			Load <='0';
		else
			Cnt <= Cnt +1;
			Load <='1';
		end if;	
	end if;
end process;

end Behavioral;