int.vhd.bak

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity int is port(
	  lint              : in std_logic;
	  clk,rst           : in std_logic;
	  lint1,lint2       : buffer std_logic;
	  ready             : in std_logic;
      ccs,ads,blast,wr  : out std_logic;
      la                : out std_logic_vector(31 downto 2);
      ld_in             : in  std_logic_vector(31 downto 0);
      ld_out            : out  std_logic_vector(31 downto 0);
	  s1,s2:              out std_logic
	  
);
end int;

architecture a of int is
type state1 is (idle,r1,r2,r3,r4,w0,w1,w2,w3,done2,zz);
signal state :state1;
signal tempd1 :std_logic_vector(31 downto 0);
signal count : std_logic_vector(27 downto 0);
signal t_din,t_dout,tt :std_logic_vector(31 downto 0);
signal tc:std_logic_vector(1 downto 0);
--signal s1,s2:std_logic;
begin
t_din<=ld_in;
ld_out<=t_dout;

process(clk,rst)
begin
     if rst='0' then
       state<=idle;tc<="00";
      count<="0000000000000000000000000000";
      s1<='0';s2<='0';
     elsif clk'event and clk='1' then
       case  state is
           when idle=>
                         ccs<='Z';ads<='Z';blast<='Z';wr<='Z';lint1<='1';
                         la(31 downto 2)<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";s1<='0';s2<='0';
                         if lint='0'  then  --int1 is a one clk pulse
                             state<=r1;
                         else
                             state<=idle;
                         end if;
                when r1=>
                         ccs<='0';ads<='0';wr<='0';state<=r2;
                         la(31 downto 2)<="000000000000000000000000110010";--C8
				when r2=>
                         ccs<='1';ads<='1';blast<='0';
                         s1<='1';
                		 state<=r3;
                when r3=>
                         state<=r4;
                when r4=>
                         if ready='0' then 
                            tempd1<=t_din;
                            blast<='1';
                            state<=zz;
                            
                         else
                            state<=r4;
						 end if;
              when zz=> s1<='0';
                         --count<=count+1;
                          --if count=X"FFFFFFF" then
	                      --       count<=X"0000000";
	                             state<=w0;
	                     -- end if;
                         --  s2<='1';
                          
                when w0=>
                         ccs<='0';ads<='0';wr<='1';state<=w1;
                         la(31 downto 2)<="000000000000000000000000111000";--CC
				when w1=>
                         ccs<='1';ads<='1';blast<='0';state<=w2; 
                         t_dout<=tempd1;  -- "11000000000000000000000000001110"; --     
                when w2=>
                         state<=w3;
                when w3=>
                         if ready='0' then 
                            blast<='1';
                            state<=done2;
                            
                         else
                            state<=w3;end if;
               when done2=>
                       if lint='1' then 
                         state<=idle;
                       end if; 
                       lint1<='0';
       end case;
    end if;
   
end process;

end a;