read.vhd

altera公司的FPGA的一些开发用的VHDL的源代码用于学习

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

entity read is port(
		clk,rst,lint2,wrfull: in std_logic;
		ads,blast,wr,waitt,wrreq:out std_logic;
		ready : in std_logic;
		--ld    : in std_logic_vector(31 downto 0);
		la    : out std_logic_vector(31 downto 2)
);
end read;

architecture a of read is
type state1 is (idle,r0,r1,r2,r3,r4);
signal state :state1;
signal count : std_logic_vector(22 downto 0);
begin
process(rst,clk)
begin
     if rst='0' then
       ads<='Z';blast<='Z';wr<='1';waitt<='Z';wrreq<='0';la(31 DOWNTO 2)<="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
       state<=idle;
       count<="00000000000000000000000";
     elsif clk'event and clk='1' then
       case state is
            when idle=>
                       if lint2='0' then
                           state<=r0;
                       else
                           state<=idle;
                       end if;
            when r0  =>
                       ads<='1';blast<='1';wr<='1';waitt<='1';
                       state<= r1;
            when r1  =>
                       ads<='0';blast<='1';wr<='0';waitt<='1';
                       --la(31 downto 2)<="  ";
                       state<= r2;
            when r2  =>
                       ads<='1';
                       state<= r3;
            when r3  =>
                       if ready='0' then
                          wrreq<='1';
                          state<=r4;
                          count<=count+1;
                       else
                          wrreq<='0';
                          state<=r3;
                       end if;
            when r4  =>
                       if ready='0' and wrfull='0' then
                          wrreq<='1';
                          count<=count+1;
                          --if count="00000000000000010000000 " then
                       else
                          wrreq<='0';
                          waitt<='0';
                       end if;
         end case;
    end if;                    
end process;     
end a;