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mimasuo.vhf
-- VHDL model created from mimasuo.sch - Thu Apr 19 19:18:50 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vc
clk_divide_3.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY clk_divide_3 IS
PORT
(
clkin ,rst: IN STD_LOGIC;
clkout : OUT STD_LOGIC;
t1,t2: out std_logic
);
END clk_divide_3;
mux2_1.vhd
--core_design
--mux2_1
--all right reserved
library ieee;
use ieee.std_logic_1164.all;
entity mux2_1 is
port (en:in std_logic;
in1:in std_logic_vector(31 downto 0);
in2:in std_logi
dds.vhd
--DDS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS
PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
EN:IN STD_LOGIC;
RESET:IN STD_LOGIC;
sum99.vhd
--SUM910.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUM99 IS
PORT(K: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
CLK: IN STD_LOGIC;
EN: IN STD_L
imagexlib_arch.vhd
--*******************************************************************
-- Copyright(C) 2005 by Xilinx, Inc. All rights reserved.
-- This text/file contains proprietary, confidential
-- information o
songer.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS -- 顶层设计
PORT ( clk : in std_logic;
CODE1 : OUT std_logic_vector(2 dow
mux48.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MUX48 IS
PORT ( S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A2 : IN STD_LOGIC_V
mux41s.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41S IS
PORT (S1,S2 : IN STD_LOGIC ;
A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
mux48.vhd
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY MUX48 IS
PORT ( S : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
A1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A2 : IN STD_LOGIC_V