mux2_1.vhd

来自「几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码」· VHDL 代码 · 共 28 行

--core_design
--mux2_1
--all right reserved

library ieee;
use ieee.std_logic_1164.all;

entity mux2_1 is
  port (en:in std_logic;
  	in1:in std_logic_vector(31 downto 0);
  	in2:in std_logic_vector(31 downto 0);
  	out1:out std_logic_vector(31 downto 0)
       );
end mux2_1;

architecture b of mux2_1 is
begin
process(en,in1,in2)
begin
case en is
when '0' =>out1<=in1;
when '1' =>out1<=in2;
when others =>null;
end case;
end process;
end b;