control.vhd

来自「几个VHDL的源代码和和一个本人编写的5级流水线RISC CPU的代码」· VHDL 代码 · 共 174 行

--core_design
--control
--all right reserved

library ieee;
use ieee.std_logic_1164.all;

entity control is
  port (reset:in std_logic;
  	op : in std_logic_vector (5 downto 0);         	-- The op code
	memread:out std_logic;
	memwrite:out std_logic;
	memtoreg:out std_logic;
	pcsource:out std_logic;
	ALUop:out std_logic_vector(2 downto 0);
	ALUsrcB:out std_logic_vector(1 downto 0);
	ALUsrcA:out std_logic_vector(1 downto 0);
	ALUsrc:out std_logic;
	inv_in2:out std_logic;
	regdst:out std_logic;
	regwrite:out std_logic
       );
  end control;

architecture ctl of control is
begin
process(op,reset)
 begin
  if reset='1' then
     ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='0';
    ALUop<="000";
    inv_in2<='0';
    memread<='0';
    memwrite<='0';
    memtoreg<='0';
    pcsource<='1';
    regdst<='0';
    regwrite<='0';
  elsif reset='0' then
  case op is
   when "100000" =>  --ADD
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='0';
    ALUop<="001";
    inv_in2<='0';
    memread<='0';
    memwrite<='0';
    memtoreg<='1';
    pcsource<='1';
    regdst<='1';
    regwrite<='1';
   
   when "100010" =>  --SUB
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='0';
    ALUop<="010";
    inv_in2<='1';
    memread<='0';
    memwrite<='0';
    memtoreg<='1';
    pcsource<='1';
    regdst<='1';
    regwrite<='1';
   
   when "100100" =>  --AND
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='0';
    ALUop<="100";
    inv_in2<='0';
    memread<='0';
    memwrite<='0';
    memtoreg<='1';
    pcsource<='1';
    regdst<='1';
    regwrite<='1';
   
   when "100101" =>  --OR
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='0';
    ALUop<="011";
    inv_in2<='0';
    memread<='0';
    memwrite<='0';
    memtoreg<='1';
    pcsource<='1';
    regdst<='1';
    regwrite<='1';
   
   when "101010" =>  --XOR
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='0';
    ALUop<="101";
    inv_in2<='0';
    memread<='0';
    memwrite<='0';
    memtoreg<='1';
    pcsource<='1';
    regdst<='1';
    regwrite<='1';
  
  when "101100" =>  --store word
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='1';
    ALUop<="001";
    inv_in2<='0';
    memread<='0';
    memwrite<='1';
    memtoreg<='0';
    pcsource<='1';
    regdst<='Z';
    regwrite<='0';
  
  when "101101" =>  --load word
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='1';
    ALUop<="001";
    inv_in2<='0';
    memread<='1';
    memwrite<='0';
    memtoreg<='0';
    pcsource<='1';
    regdst<='0';
    regwrite<='1';
  
  when "010000" =>  --branch**
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='1';
    ALUop<="001";   --AND
    inv_in2<='0';
    memread<='0';
    memwrite<='0';
    memtoreg<='0';
    pcsource<='0';  --*
    regwrite<='0';
    
  when "010001" =>  --jump**
    ALUsrcA<="00";
    ALUsrcB<="00";
    ALUsrc<='1';
    ALUop<="011";   --NOP
    inv_in2<='0';
    memread<='0';
    memwrite<='0';
    memtoreg<='0';
    pcsource<='1';  --*
    regwrite<='0';
  
  when "000000" =>  --NOP
    ALUsrcA<=(others=>'Z');
    ALUsrcB<=(others=>'Z');
    ALUsrc<='Z';
    ALUop<="000";   --NOP
    inv_in2<='0';
    memtoreg<='Z';
    memread<='Z';
    memwrite<='Z';
    pcsource<='1';
    regdst<='Z';  
    regwrite<='0';
  when others => null;
  end case;
end if;
end process;
end ctl;