songer.vhd

总体演示程序DEMO_FPGA.rar

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Songer IS                                     -- 顶层设计
    PORT (     clk    : in  std_logic; 
               CODE1  : OUT std_logic_vector(2 downto 0);
               HIGH1  : OUT STD_LOGIC; 
             SPKOUT   : OUT STD_LOGIC );
 END;
ARCHITECTURE one OF Songer IS
    COMPONENT NoteTabs
        PORT (   clk  : IN STD_LOGIC;
            ToneIndex : OUT INTEGER RANGE 0 TO 15  );
    END COMPONENT;
    COMPONENT ToneTaba
        PORT ( Index :  IN INTEGER RANGE 0 TO 15;
               CODE  : OUT std_logic_vector(2 downto 0);
               HIGH  : OUT STD_LOGIC; 
               Tone : OUT INTEGER RANGE 0 TO 16#7FF#   );  --11位2进制数
    END COMPONENT;
    COMPONENT Speakera
        PORT (  clk  : IN STD_LOGIC;
          Tone : IN INTEGER RANGE 0 TO 16#7FF#;             --11位2进制数
          SpkS : OUT STD_LOGIC  );
    END COMPONENT;
	 component mhz_generator
	 Port ( clk : in std_logic;
           clk_12MHz : out std_logic;
			  clk_8Hz   : out std_logic);
	 end component;
    SIGNAL Tone : INTEGER RANGE 0 TO 16#7FF#;
    SIGNAL ToneIndex : INTEGER RANGE 0 TO 15;
	 signal a,b:std_logic;
BEGIN
                    -- 安装U1, U2, U3
u0: mhz_generator port map(clk=>clk,clk_12MHz=>a,clk_8Hz=>b);
u1 : NoteTabs  PORT MAP (clk=>b, ToneIndex=>ToneIndex);
u2 : ToneTaba PORT MAP (Index=>ToneIndex, Tone=>Tone,CODE=>CODE1,HIGH=>HIGH1);
u3 : Speakera PORT MAP(clk=>a,Tone=>Tone, SpkS=>SPKOUT );
END;