mux41s.vhd

来自「Alera 的8051 IP core的示例文件5个」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41S IS
    PORT (S1,S2 : IN STD_LOGIC ; 
          A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  
          B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          C : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  
          D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  
       QOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  
        );
END MUX41S;
ARCHITECTURE behav OF MUX41S IS
SIGNAL  S : STD_LOGIC_VECTOR(1 DOWNTO 0);
  BEGIN
    S<= S1&S2; 
  QOUT <= A WHEN S="00"  ELSE
          B WHEN S="01"  ELSE
          C WHEN S="10"  ELSE
          D ;
END behav;