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找到约 10,000 项符合
Logic Analyzer 的代码
timer_set.vhd
----------------------------- timer_set.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-----------------------------------------
counter24.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter24 is
port ( cp:in std_logic;
bin:out std_logic_vector(5 downto 0
txunit.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TxUnit is
port (
Clk : in std_logic; -- Clock signal
Reset : in std_logic; -- Reset input
Enable : in std_logic; -- Enable
mult8x8.vhd
library ieee;
use ieee.std_logic_1164.all;
entity mult8x8 is
port(clk:in std_logic;
start:in std_logic;
a:in std_logic_vector(7 downto 0);
b:in std_logic_vector(7 downto 0);
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXXXX
pingpanggame.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pingpanggame IS
PORT(clk_4mhz:IN STD_LOGIC;
playr:IN STD_LOGIC;
playl:IN STD
cpu.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:42:51 10/19/05
-- Design Name:
-- Module Name: cpu - Be
sorter.vhd
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-- entity = sorter --
-- version = 1.0 --
-- last update = 20/06/05 --
-- author = Jose Nunez --
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sorter.vhd.bak
--------------------------------------
-- entity = sorter --
-- version = 1.0 --
-- last update = 20/06/05 --
-- author = Jose Nunez --
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