counter24.vhd

来自「实现一个简单的电子钟」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter24 is
port ( cp:in std_logic;
       bin:out std_logic_vector(5 downto 0);
       s,clr,ec:in std_logic;
       cy24:out std_logic
       
      );

end counter24;

architecture a of counter24 is

 signal q:std_logic_vector(4 downto 0);
signal rst,dly:std_logic;

begin
process(cp,rst)
        begin
  if  cp'event and cp='1' then
       if (rst='1' or q=24)  then
         q<="00000";
  elsif  ec='1'  then 
            q<=q+1;
          end if;
          end if;
        
         end process;
  
         cy24<='1' when q=24 ELSE
              '0';

       rst<='1'when (q=24 or clr='1')else 
              '0';
  
         bin<=('0'&q) when s='1'else"000000";
        
         end a;