cpu.vhd

用VHDL 编写的一个16位的cpu 设计方案

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-- Company: 
-- Engineer:
--
-- Create Date:    18:42:51 10/19/05
-- Design Name:    
-- Module Name:    cpu - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity cpu is
port(rst,clk: in	std_logic;
     DBUS:inout std_logic_vector(15 downto 0);
	b4,b3,b2,b1,b0,a7,a6,a5,a4,a3:out std_logic;
	ABUS,s0,s2:out std_logic_vector(15 downto 0);
	s4,s5:out std_logic_vector(7 downto 0);
	nMREQ,nRD,nWR,nBHE,nBLE:out std_logic);
end cpu;

architecture Behavioral of cpu is
component timer is
port( clk,rst:in std_logic;
	ex,b0,b1,b2,b3,b4:out std_logic;
      t:out std_logic_vector(2 downto 0));
end component timer;
component GetInstr is
port(
	clk,clr,rz,ex: in std_logic;
	t: in std_logic_vector( 2 downto 0 );	  --高1位代表周期，低3位代表阶段
	r7:  in std_logic_vector(  7 downto 0 );
	s4,s5:out std_logic_vector(  7 downto 0 );	  --
	mar: out std_logic_vector( 15 downto 0 );	  --地址
	mdrin:in std_logic_vector( 15 downto 0 );
	mdrout:out std_logic_vector(15 downto 0);	  --数据
	rd,wr: out std_logic;			
	opcode :buffer std_logic_vector( 3 downto 0 );
	r1, r2 : out std_logic_vector( 2 downto 0 );
	imm : buffer std_logic_vector( 7 downto 0 )
	);
end component GetInstr;
component exe is
port( clk,ex:in std_logic;
      opcode:in std_logic_vector(3 downto 0);
	 r1,r2,t:in std_logic_vector(2 downto 0);
	 imm:in std_logic_vector(7 downto 0);
	 r7:out std_logic_vector(7 downto 0);
	 mar:out std_logic_vector(15 downto 0);
	 mdrin:in std_logic_vector(15 downto 0);
	 mdrout:out std_logic_vector(15 downto 0);
	 
	 rd,wr,rz:out std_logic);
end component exe;
component memcontrol is
port( t:in std_logic_vector(2 downto 0);
    	clk,rd1,wr1,rd2,wr2,ex:in std_logic;
		mdr0out,mdr1out,ABUS,s0,s2:out std_logic_vector(15 downto 0);
		mdr0in,mdr1in,mar0in,mar1in:in std_logic_vector(15 downto 0);
		DBUS:inout std_logic_vector(15 downto 0);
		--:buffer std_logic;
		nMREQ,nRD,nWR,nBHE,nBLE,a7,a6,a5,a4,a3:out std_logic);
end component memcontrol;
signal mar0,mdr0in,mdr0out,mar1,mdr1in,mdr1out:std_logic_vector(15 downto 0);
signal ex,rz,rd1,wr1,rd2,wr2:std_logic;
signal t,r1,r2:std_logic_vector(2 downto 0);
signal r7,imm:std_logic_vector(7 downto 0);
signal opcode:std_logic_vector( 3 downto 0 ); 
begin
	 u1:timer port map( clk,rst,ex,b0,b1,b2,b3,b4,t);
	 u2:GetInstr port map(clk,rst,rz,ex,t,r7,s4,s5,mar0,mdr0in,mdr0out,rd1,wr1,opcode,r1, r2,imm);
	 u3:exe port map( clk,ex,opcode,r1,r2,t,imm,r7,mar1,mdr1in,mdr1out,rd2,wr2,rz);
	 u4:memcontrol port map(t,clk,rd1,wr1,rd2,wr2,ex,mdr0in,mdr1in,ABUS,s0,s2,mdr0out,mdr1out,mar0,mar1,DBUS,nMREQ,nRD,nWR,nBHE,nBLE,a7,a6,a5,a4,a3);

     
end Behavioral;