sorter.vhd.bak

这个是Xilinx编程的源码

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--  entity       = sorter           --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
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-- top of the hierarchy sorter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity sorter is
port
(	
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	nrdy : in std_logic;
	reset : in std_logic;
	new_sort : in std_logic;
	clear : in std_logic;
	nack : out std_logic;
	data_middle : out std_logic_vector(3 downto 0)
);
end sorter;

architecture struct of sorter is

-- compare two number component, EQ output not used

component comparator
   port (
	  indata_a : in std_logic_vector(3 downto 0);
	  indata_b : in std_logic_vector(3 downto 0); 
	  lt : out std_logic; -- less than
	  eq : out std_logic  -- equal 	  
    );
end component; 

component register_file 
port
(
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	srd : in std_logic_vector(2 downto 0); -- read address
	enwr : in std_logic; -- enable write
	swr : in std_logic_vector(2 downto 0); -- write address
	clear : in std_logic; -- general asyncronous reset
	reset : in std_logic; --general syncronous reset
	new_sort : in std_logic; -- clear register file to start sorting new numbers
	data_middle : out std_logic_vector(3 downto 0); -- register number 2 output
	data_out : out std_logic_vector(3 downto 0) -- output to the comparator
);
end component;

component state_machine 
 port ( clk : in std_logic;
        clear : in std_logic;
        reset : in std_logic;
        nrdy : in std_logic; -- enable active low
        lt : in std_logic; -- less than active
        eq : in std_logic;
        srd : out std_logic_vector(2 downto 0); -- address to read register file
        swr : out std_logic_vector(2 downto 0); -- address to write register file
        inp : out std_logic; -- select input for register file
        enwr : out std_logic; -- enable write register file
        nack : out std_logic -- done when low
      );
end component;  

signal r_di, r_do : std_logic_vector(3 downto 0); --input and ouput of register file
signal srd, swr : std_logic_vector(2 downto 0); -- read and write address for register file
signal lt,eq, inp, enwr : std_logic; -- control signals 


begin    

-- add code here

end struct;  -- end of architecture