state_machine.vhd

来自「这个是Xilinx编程的源码」· VHDL 代码 · 共 45 行

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--  entity       = state_machine           --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
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-- main control unit for the sorting process

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_STD.all;


entity state_machine is
 port ( clk : in std_logic;
        clear : in std_logic;
        reset : in std_logic;
        nrdy : in std_logic; -- enable active low
        lt : in std_logic; -- less than active
        eq : in std_logic;
        srd : out std_logic_vector(2 downto 0); -- address to read register file
        swr : out std_logic_vector(2 downto 0); -- address to write register file
        inp : out std_logic; -- select input for register file
        enwr : out std_logic; -- enable write register file
        nack : out std_logic -- done when low
      );
end;  

architecture struct of state_machine is

-- add code here

end;